Nvidia Corporation

David B Kirk

John Erik Lindholm

Simon S Moy

Matthew Nicholas Papakipos

John Stephen Montrym

Paolo Enrique Sabella

Douglas A Voorhies

Nicholas J Foskett

Kevin Dawallu

Mingjian Yang

Curtis R Priem

Rui Bastos

Henry Packard Moreton

Walter E Donovan

Harold Robert Feldman Zatz

Steven E Molnar

Larry I Gritz

Daniel Elliott Wexler

Gopal Solanki

Jonathan Rice

Brett Coon

Emmett Michael Kilgariff

Sean Jeffrey Treichler

John M Danskin

Joe L Yeun

Mark J Kilgard

Gerrit Ary Slavenburg

David Cook

Chris A Malachowsky

Thomas Francis Fox

Liang Peng

Shaun Ho

David Schmenk

Steven E Moinar

Charles M Flaig

Pao Sabella

A display for a computer system, such as an LCD, is configured to consume less power when compared to conventional designs. The display includes a screen and at least one backlight configured to illuminate the screen. An input to the at least one backlight is adjustable to produce a desired level of brightness. The input may be computed based on a generated source image and a defined constraint. An input to the display is computed based on the input to the at least one backlight and the source image. The input to the display modifies the level of brightness provided by the at least one backlight to produce a viewable image.

Variable brightness LCD backlight

A system, method, and computer program product are provided for controlling stereo glasses shutters. In use, a right eye shutter of stereo glasses is controlled to switch between a closed orientation and an open orientation. Further, a left eye shutter of the stereo glasses is controlled to switch between the closed orientation and the open orientation. To this end, the right eye shutter and the left eye shutter of the stereo glasses may be controlled such that the right eye shutter and the left eye shutter simultaneously remain in the closed orientation for a predetermined amount of time.

System, method, and computer program product for controlling stereo glasses shutters

A method and system are disclosed for antialiased rendering a plurality of pixels in a computer system. The method and system comprise providing a fixed storage area and providing a plurality of sequential format levels for the plurality of pixels within the fixed storage area. The plurality of format levels represent pixels with varying degrees of complexity in subpixel geometry visible within the pixel. A system and method in accordance with the present invention provides at least the following format levels: one-fragment format, used when one surface fully covers a pixel; two-fragment format, used when two surfaces together cover a pixel; and multisample format, used when three or more surfaces cover a pixel. The method and system further comprise storing the plurality of pixels at a lowest appropriate format level within the fixed storage area, so that a minimum amount of data is transferred to and from the fixed storage area. The method and system further comprise procedures for converting pixels from one format level to take into account newly rendered pixel fragments. All formats represent depth values in a consistent manner so that fragments rendered during later rendering passes match depth values resulting from rendering the same primitive in earlier passes. Thus, the invention enables high-quality antialiasing with minimal data transferred to and from the fixed storage area, while supporting multi-pass rendering.

Method and system for efficient antialiased rendering

A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

System, method and article of manufacture for a programmable processing model with instruction set

Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.

Hierarchical processor array

Digital Image compositing using a programmable graphics processor is described. The programmable graphics processor supports high-precision data formats and can be programmed to complete a plurality of compositing operations in a single pass through a fragment processing pipeline within the programmable graphics processor. Source images for one or more compositing operations are stored in graphics memory, and a resulting composited image is output or stored in graphics memory. More-complex compositing operations, such as blur, warping, morphing, and the like, can be completed in multiple passes through the fragment processing pipeline. A composited image produced during a pass through the fragment processing pipeline is stored in graphics memory and is available as a source image for a subsequent pass.

Digital image compositing using a programmable graphics processor

Apparatuses and methods for detecting position conflicts during fragment processing are described. Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after write) hazard may exist. A RAW hazard exists when there is a pending write to a destination location that source data will be read from during execution of the program. When the fragment enters a processing pipeline, each destination location that may be written during the processing of the fragment is entered in conflict detection unit. During processing, the conflict detection unit is updated when a pending write to a destination location is completed.

Methods of processing graphics data including reading and writing buffers

A system for providing a command stream that includes a controller chip is disclosed. The controller chip includes an engine operative to manage a memory. The engine includes an interface. A storage element is coupled to the engine and the storage element is accessible by a central processing unit (CPU) through the engine. The engine receives commands from the CPU via the interface, manages the storage element via the interface and writes the commands into the memory. The engine incorporates the storage element as part of the memory.

Graphic controller to manage a memory and effective size of FIFO buffer as viewed by CPU can be as large as the memory

Growing community of inventors

Santa Clara, CA, United States of America

David B Kirk