Intel Corporation

David B Jackson

Bret L Toll

Scott Dion Rodgers

Frank Binns

James S Coke

Peter J Ruscito

Masood Tahir

Ves A Naydenov

William W Macy, Jr

Eric L Debes

Robert L Farrell

Jonathan Jay Tyler

Mitchell Diamond

Ki W Yoon

Vesselin Naydenov

Mohammad A Abadallah

Kip A Baumann

Rafi M Saied

A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

Length determination of instruction code with address form field and escape opcode value by evaluating portions other than instruction specific opcode

Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode

Determining length of instruction with escape and addressing form bytes without evaluating opcode

Determining length of instruction with multiple byte escape code based on information from other than opcode byte

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.

Method and apparatus for performing multiply-add operations on packed byte data

Techniques for control word prediction and speculative execution. In one embodiment, an apparatus includes a control word predictor, execution resources, and a comparison module. The control word predictor of this embodiment predicts a predicted control word for execution of operations in response to a control word changing operation. The execution resources of this embodiment speculatively execute the plurality of operations utilizing the predicted control word, and the comparison module determines if the predicted control word matches an actual control word set by the control word changing operation or a plurality of other control words, and to cause re-execution of said plurality of operations if said actual control word matches any of the plurality of other control words.

Control word prediction and varying recovery upon comparing actual to set of stored words

Growing community of inventors

Foslom, CA, United States of America

David B Jackson