Hewlett-packard Company

Hewlett-packard Development Company, L.p.

David B Hollenbeck

Johnny Q Zhang

David W Quint

William S Worley, Jr

Kent R Townley

Li Ching Tsai

Timothy L Michalka

Josef A Dvorak

Ricky L Pettit

A clock buffer circuit having a reduced propagation delay therethrough. The clock buffer circuit has a clock input for receiving an initial clock pulse thereto, and a clock output for transmitting a buffered clock pulse therethrough. A first driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from a low voltage level to a high voltage level. A second driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from the high voltage level to the low voltage level. A holder circuit and a first and trigger circuit for the second driver chain are also included.

Clock buffer circuit having short propagation delay

An apparatus for producing one or more clock signals comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A clock signal fed through the plurality of delay elements produces multiple delayed versions of the clock signal. Logic circuitry selects and combines the delayed clock signal versions to produce one or more output clock signals, each having a frequency that is a selected fraction of the input clock signal. An associated method delays the input clock signal N times sequentially for a natural number N. then selects a series of time splices of the delayed clock signals to produce an output clock signal. In some implementations the input clock signal can be referenced to a reference clock signal. The output clock signal frequency can be set to (N/M)&times;f , for a natural number M and reference clock signal frequency f . The apparatus and associated method can flexibly produce a large variety of output clock frequencies and frequency ratios, lock to f with a dynamic response independent of the output frequency range and can be optimized to a single reference frequency, need not relock to change output frequency, and reduce clock skew.

Input clock delayed by a plurality of elements that are connected to logic circuitry to produce a clock frequency having a rational multiple less than one

A termination structure is shown whereby multiple transmission lines designed to have the same intrinsic impedance and same delay are driven from a central node. The central node is driven by a driver and calibration resistor connected in series to produce a drive impedance that is equal to the parallel combination of the intrinsic impedances of the multiple transmission lines. At the other end of the multiple transmission lines is a receiver and a feedback circuit. The feedback circuit provides a modest amount of positive feedback from the output of the receiver to the input of the receiver. This positive feedback prevents the output of the receiver from being affected by small reflections and perturbations that result from mismatches among the multiple transmission lines.

Termination structure based on the cancellation of the reflected wave

Signal delay and skew within an integrated circuit are minimized when 1) signals are distributed to distant points of an integrated circuit via a layer of its package, and 2) traces in the package layer are etched and treated as transmission lines. As disclosed herein, a signal is driven through a first connection between an integrated circuit and an integrated circuit package layer. The signal is then distributed to one or more additional connections between the integrated circuit and the integrated circuit package layer, by means of point-to-point transmission lines formed in the integrated circuit package layer, each of the transmission lines being terminated at one or both ends by impedances which are substantially matched to the characteristic impedance of the transmission line to which they are attached. The signal is then received into the integrated circuit through the one or more additional connections between the integrated circuit and the integrated circuit package layer.

Package routing of integrated circuit signals

A ring-type signal controlled oscillator comprising a series of active delay elements, each including a respective differential pair of transistors. The inputs and outputs of the differential pair transistors are interconnected in a closed ring to produce oscillations at a frequency determined by the delay of each delay element. The differential pair of transistors further has a pair of current source inputs for controlling an amount of delay of the delay element, and a pair of load inputs for stabilizing the amount of delay. The invention advantageously provides high frequency operation with substantially symmetric rise and fall time, while limiting spread in oscillation frequency and spread in amplitude in relation to fabrication process variability and power supply variability.

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Windsor, CO, United States of America

David B Hollenbeck