Mostek Corporation

Srx Corporation

Honeywell G.m.b.h.

David B Hildebrand

Charles B Johnson

Jeffrey L Box

Ian A Young

Robert M Gemmell

Michael J Caruso

David E Karoly

Kul B Ohri

A distributed switching system (20) is provided for implementation in an integrated circuit utilizing a switching bus (30) in which bus lines (30a-30n) are time division multiplexed serial data streams consisting of time slots used for both transmit and receive directions. The bus lines (30a-30n) comprise a single bi-directional bus used for both inter-processor communication and for transparent voice and data switching. The distributed switching system (20) includes a bus line selector (31) to select one of the plurality of bus lines (30n-30n) to perform space switching functions. A slot counter (32) is provided for selecting one of a plurality of time slots on the plurality of bus lines (30n-30n) to perform a time switching function. Interface shift registers (33, 35) are interconnected for transmitting to and receiving data from the switching bus (30). Interconnected to the bus registers (33, 35) is a line interface register (34) for transmitting to and receiving data from a digital instrument.

Distributed switching system

A distributed switching system (20) is provided for implementation in an integrated circuit utilizing a switching bus (30) in which bus lines (30a-30n) are time division multiplexed serial data streams consisting of time slots used for both transmit and receive directions. The distributed switching system (20) includes a bus line selector (31) to select one of the plurality of bus lines (30a-30n) to perform space switching functions. A slot counter (32) is provided for selecting one of a plurality of time slots on the plurality of bus lines (30a-30n) to perform a time switching function. Interface shift registers (33, 35) are interconnected for transmitting to and receiving data from the switching bus (30). Interconnected to the bus registers (33, 35) is a line interface register (34) for transmitting to and receiving data from a digital instrument.

A pipelined multiplexer is provided for selecting one-of-m input signals, comprising N stages of select elements, each stage of the select elements including 2.sup.n /2 select gates, where n is the stage number. Each select gate has two input terminals and one output terminal for selecting one of two input signals from the input terminals. The selection of an input signal is in response to a corresponding select control signal and the outputting of the respective selected signal is in response to a clocking signal.

Pipeline multiplexer

A compensated current reference circuit (10) includes bipolar transistors (32, 48) which have corresponding base-to-emitter resistors (36, 52). A bipolar transistor (70) and associated circuitry produces a variable amplitude tail current which has a predetermined temperature coefficient and regulates the current flow through the bipolar transistors (32, 48). The combination of tail current for the transistor (48) and the impedance size of its corresponding resistor (52) are adjusted to produce a reference current through a transistor (44) which has a relatively large negative temperature coefficient. The bipolar transistor (32) and its associated base-to-emitter resistor (36) together with the tail current through transistor (38) are adjusted such that a current through transistor (22) is produced which has a relatively small negative temperature coefficient. The difference of these currents is produced through a transistor (18) to produce a reference current having a relatively small controlled temperature coefficient. The control voltage at node (96) is provided to a transistor (81) to produce a stable reference current therethrough. The selection of appropriate values for tail currents and the base-to-emitter resistor impedances for the bipolar transistors (32, 48) can produce any of a wide range of values of temperature compensated currents. The reference currents are also mirrored to a node (100) and summed to produce an output current having a desired temperature coefficient which is in turn passed through a resistor (116) to produce a temperature compensated voltage at a node (94).

Temperature compensated reference circuit

A bandgap voltage reference employing only subsurface currents wich may be fabricated using a standard CMOS process. The reference includes first and second vertical bipolar transistors having common collectors formed in an integrated circuit substrate. A first resistor connects the emitter of the first transistor to ground potential. A second resistor connects the emitter of the second transistor to a reference node while a third resistor connects the reference node to ground. A differential amplifier has a positive input connected to the reference node, a negative input connected to the first transistor emitter and an output connected to the bases of the first and second transistors and also providing the reference voltage output. In a preferred form the output of the differential amplifier is buffered by a third transistor and coupled by a resistive divider to the first and second transistor bases so that the reference voltage may be selected at any scalar of the basic bandgap voltage.

Bandgap voltage reference employing sub-surface current using a standard

A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge transistor (30) is interconnected to the voltage supply (V) and is clocked by the first clock phase. A discharge transistor (32) is interconnected to the precharge transistor (30) thereby defining a first node (A) and is clocked by the second clock phase to conditionally discharge the first node (A). An input logic circuit (34) is interconnected to the discharge transistor (32) thereby defining a second node (B) for providing a discharge path from the first node (A) to a ground voltage potential, the input logic circuit (34) is connected to receive the input signal. An output transistor (36) is interconnected to the first node (A) for generating the delayed output signal. The output transistor (36) is clocked by the second clock phase. A capacitor (38) is interconnected to the first node (A) and the output transistor (36) and is clocked by the second clock phase for maintaining the first node (A) at a predetermined voltage level by a bootstrapping operation.

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Bedford, TX, United States of America

David B Hildebrand