Intel Corporation

Motorola Corporation

Freescale Semiconductor,inc.

Fujitsu Semiconductor Limited

David B Harnishfeger

Claudio Gustavo Rey

Kris Kaufman

Merit Y Hong

Daniel B Schwartz

Daniel E Brueske

Frederick L Martin

Byron G Bynum

Bing Xu

Mark Alan Kirschenmann

George Norris

Gordon H Allen

Kristopher Kevin Kaufman

Darin Nguyen

Jeffrey D Ganger

Michael J Pennell

Stephen T Machan

Kaveh Parsi

A circuit may include a digitally-controlled oscillator including a coarse frequency-tuning array with a multiple selectable coarse frequency-tuning segments. Each of the coarse frequency-tuning segments may have a coarse segment frequency step size. The digitally-controlled oscillator may also include a fine frequency-tuning array with multiple selectable fine frequency-tuning segments. The fine frequency-tuning array may have a fine array frequency step size that is at least twice the coarse segment frequency step size. The digitally-controlled oscillator may be configured to generate an output signal with a frequency based on the coarse frequency-tuning array and the fine frequency-tuning array.

Adjusting tuning segments in a digitally-controlled oscillator

A temperature measurement system is disclosed. In accordance with some embodiments of the present disclosure, a temperature measurement system may comprise a resistor, a thermistor, a resistance-to-current converter configured to generate a current signal based on a resistance, an analog-to-digital converter (ADC) configured to receive a first current signal based on the resistor, convert the first current signal into a first digital signal, receive a second current signal based on the thermistor, and convert the second current signal into a second digital signal, and a calculation stage communicatively coupled to an ADC output and configured to determine a first digital value based on the first digital signal, determine a second digital value based on the second digital signal, calculate a resistance ratio based on the first digital value and the second digital value, and determine a temperature output value based on the resistance ratio.

Temperature measurement system

In accordance with some embodiments of the present disclosure, a calibrated temperature measurement system comprises a resistor, a thermistor, a resistance-to-current converter configured to generate a current signal based on a resistance, and an analog-to-digital converter (ADC) configured to receive a first current signal based on the resistor, convert the first current signal into a first digital signal, receive a second current signal based on the thermistor, and convert the second current signal into a second digital signal. A memory may comprise resistor-characterization information. A calculation stage communicatively coupled to an ADC output may be configured to determine a first digital value based on the first digital signal, determine a second digital value based on the second digital signal, calculate a resistance ratio based on the first digital value and the second digital value, and determine a temperature output value based on the resistance ratio and the resistor-characterization information.

Calibrated temperature measurement system

A temperature-measurement input stage may include a resistor, a thermistor, a first multiplexor, an amplifier, a second multiplexor, and an output stage. The first multiplexor may be configured to couple the resistor to a first amplifier input during a first multiplexor state, and couple the thermistor to the first amplifier input during a second multiplexor state. The amplifier may comprise the first amplifier input, a second amplifier input coupled to a voltage reference, and an amplifier output coupled to a feedback path. The second multiplexor may be configured to route a feedback current to the resistor during the first multiplexor state and route the feedback current to the thermistor during the second multiplexor state. The output stage may be configured to provide an output current based on the feedback current.

Input stage for temperature measurement system

A method may include measuring a frequency difference between an actual frequency and an expected frequency associated with a frequency control calibration signal value for each of a plurality of frequency control calibration signal values during a calibration phase. The method may additionally include generating integral non-linearity compensation values based on the frequency differences measured. The method may further include generating the applied frequency control signal based on a frequency control calibration signal value received by the digital-to-analog converter during the calibration phase. The method may also include generating a compensated frequency control signal value based on a frequency control signal value received by the integral non-linearity compensation module and an integral non-linearity compensation value associated with the frequency control signal value during an operation phase of the wireless communication element.

System and method for correcting integral nonlinearity in an oscillator system

A method of generating a transmission signal may include mixing a baseband signal assigned for transmission within a narrow frequency range ('assigned narrow frequency range') included in a wireless communication channel to produce a shifted signal. The shifted signal may have a shifted frequency that is based on a shift from the assigned narrow frequency range toward a center frequency of the wireless communication channel by a frequency offset. The method may further include shifting a modulation frequency of a modulating signal toward the assigned narrow frequency range frequency range and away from the center frequency by the frequency offset. Additionally, the method may include mixing the shifted signal with the modulating signal to produce a transmission signal having a transmission frequency within the assigned narrow frequency range.

Reducing transmission signal artifact spacing

In accordance with some embodiments of the present disclosure, a method may include determining a range of frequencies allocated to resource blocks to be transmitted during a subsequent sub-frame slot or sounding reference symbol sub-slot. The method may also include determining an approximate center frequency of the range of frequencies. The method may additionally include modulating resource blocks of the sub-frame or sounding reference symbol sub-slot at the approximate center frequency. The method may further include transmitting the modulated resource blocks at the approximate center frequency.

System and method for frequency-agile transmission in a wireless communication device

A circuit may include an oscillator configured to generate an output signal based on an analog signal and a digital signal and a controller configured to generate an offset signal based on a comparison of a first analog control signal and a second analog control signal. The circuit may also include a divider configured to generate a feedback signal based on the output signal and the offset signal. The circuit may also include an analog control signal unit configured to generate the second analog control signal based on the feedback signal and a reference signal and a coupling unit configured to select either the first analog control signal or the second analog control signal as the analog signal.

Hybrid phase-locked loops

A circuit may include a phase detector configured to generate a phase error signal based on a feedback signal and an oscillator configured to generate an output signal. The feedback signal may be based on the output signal. The circuit may also include a determination unit configured to measure a phase of the feedback signal based on the phase error signal when an output of the phase detector and an input of the oscillator are communicatively decoupled. The circuit may also include an adjustment unit configured to subtract the measured phase of the feedback signal from an intermediate signal upon which the output signal is based when the output of the phase detector and the input of the oscillator are communicatively coupled.

Reducing settling time in phase-locked loops

A method of controlling a hybrid phase-locked loop may include generating a first control signal based on an offset signal and a second control signal and determining a difference between the first and the second control signals. The method may further include adjusting a value of the offset signal based on the difference between the first and the second control signals to drive a level of the first control signal to a level of the second control signal. The method may further include determining when the level of the first control signal crosses the level of the second control signal. After the level of the first control signal crosses the level of the second control signal, the method may include adjusting the value of the offset signal based on a number of occurrences of the level of the first control signal crossing the level of the second control signal.

A method may include measuring a frequency difference between an actual frequency and an expected frequency associated with a frequency control calibration signal value for each of a plurality of frequency control calibration signal values during a calibration phase. The method may additionally include generating integral non-linearity compensation values based on the frequency differences measured The method may further include generating the applied frequency control signal based on a frequency control calibration signal value received by the digital-to-analog converter during the calibration phase. The method may also include generating a compensated frequency control signal value based on a frequency control signal value received by the integral non-linearity compensation module and an integral non-linearity compensation value associated with the frequency control signal value during an operation phase of the wireless communication element.

In embodiments of the present disclosure, a method may include determining an ambient temperature of an oscillator. The method may also include estimating an approximate frequency of operation of the oscillator. The method may additional include determining a process-based compensation to be applied to a resonator of the oscillator based on the approximate frequency. The method may further include setting a capacitance of a variable capacitor coupled to the resonator in order to compensate for temperature-dependent and process-dependent frequency variation of the oscillator based on the ambient temperature and the process-based compensation.

System and method for reducing temperature-dependent and process-dependent frequency variation of a crystal oscillator circuit

A voltage controlled oscillator (VCO) for use in a personal area network synthesizer includes a delay cell (), a first current amplifier () for amplifying an input current, a resister capacitor (RC) tuning network () for varying the amount of amplification and delay of an output of the first current amplifier. A second current amplifier () is then used for amplifying an output current from the RC tuning network. The invention includes a unique composite voltage variable capacitor (CVVC) () for precisely tuning the amount of delay presented by the delay cell. The unique topology of the delay cell () allows it to be readily used in voltage controlled oscillators (VCOs) operable at frequencies above 1 GHz.

Two port voltage controlled oscillator for use in wireless personal area network synthesizers

A system for coarsely tuning at least one voltage controlled oscillator (VCO) ( ) in a phase locked loop (PLL) synthesizer ( ) that includes a phase-frequency detector (PFD) for determining a phase difference between a VCO frequency and a reference frequency and providing an error signal if the VCO frequency and reference frequency are at least 2&pgr; radians out of phase. A monitor ( ) is then used for tracking the number of error signals produced by the PFD. The free running frequency of the VCO may be coarsely tuned in the event the monitor circuit reaches some predetermined level. The invention offers great advantage in enabling a PLL to be coarsely tuned to enable the PLL's VCO to remain with an operational range despite operational factors that effect circuit operation.

System and method for coarse tuning a phase locked loop (PLL) synthesizer using 2-PI slip detection

A differential amplitude detection circuit (10) passes the positive and negative components of a data communication differential signal through peak detector circuits (12) and (26), respectively. The peak detected voltages are held at first (15) and second (37) nodes by holding capacitors (14) and (28). Current loads (18) and (30) sink predetermined currents from the first and second nodes to prevent the peak voltages from becoming accumulated by the holding capacitors. The peak detected voltages are summed by summing circuit (21) to provide a signal V.sub.OUT that is absent of DC offset voltage errors that were present in the originally transmitted data signal. First and second resistors (36, 38) extract the common mode component of the input signal which may be subtracted from the V.sub.OUT signal for providing an error free true data output signal VTO.

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Chandler, AZ, United States of America

David B Harnishfeger