Bell Telephone Laboratories

David B Fraser

Dan Maydan

Joseph M Moran

Frederick Vratny

Roderick Kent Watts

Shyam P Murarka

Eliezer Kinsbron

Guenther Wilhelm Kammlott

Alfred Urquhart MacRae

David Yuan Lou

In a fabrication sequence for VLSI MOS devices, an advantageous alignment mark for a wafer to be directly processed by electron beam lithography is made of tantalum disilicide protected by a silicon nitride layer.

Alignment marks for electron beam lithography

A method for simultaneously patterning-over field oxide, gate oxide, and sidewall oxide--high conductivity metal-silicide electrode metallization for semiconductor integrated circuits involves (1) formation of an unpatterned polycrystalline silicon (polysilicon) layer everywhere on the exposed surface of all the oxides, (2) formation of a patterned photoresist layer on the polysilicon layer, (3) deposition of a layer of the metal-silicide over all exposed surfaces, (4) removal of the patterned photoresist layer to lift off metal-silicide, and (5) oxidation of only exposed portions of the polysilicon layer to form silicon dioxide. The polysilicon layer can be originally doped, so that the doped silicon dioxide can then be removed (without removing undoped silicon dioxide) by means of an etchant which attacks the dopant.

High conductivity metallization for semiconductor integrated circuits

It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved.

Method of fabricating high-conductivity silicide-on-polysilicon

Silicon-rich silicides of titanium and tantalum have been found to be suitable for use as the gate metal in semiconductor integrated circuits replacing polysilicon altogether. Such silicon-rich silicides, formed by sintering a cosputtered alloy with silicon to metal ratio of three as in deposited film, are stable even on gate oxide. The use of these compounds leads to stable, low resistivity gates and eliminates the need for the high resistivity polysilicon gate.

Silicon rich refractory silicides as gate metal

In an integrated circuit fabrication sequence, a relatively thick sacrificial layer (18) is deposited on a nonplanar surface of a device wafer in which high-resolution features are to be defined. The thick layer is characterized by a conforming lower surface and an essentially planar top surface and by the capability of being patterned in a high-resolution way. An intermediate masking layer (22) and then a thin resist layer (20) are deposited on the top surface of the sacrificial layer, the thickness of the resist layer being insufficient by itself to provide adequate step coverage if the resist layer were applied directly on the nonplanar surface. A high-resolution pattern defined in the resist layer is transferred into the intermediate masking layer. Subsequently, a dry processing technique is utilized to replicate the pattern in the sacrificial layer. A high-resolution pattern with near-vertical sidewalls is thereby produced in the sacrificial layer. By means of the patterned sacrificial layer, high-resolution features are then defined in the underlying nonplanar surface.

Fabrication of integrated circuits utilizing thick high-resolution

A method is disclosed for making patterned gold films in the manufacture of integrated circuit devices. The method calls for the deposition of a film of a gold compound whose heat of formation is in the range of from -20 to +10 Kcal/mole, selectively reducing the gold compound to elemental gold by irradiation, and chemically removing the unreduced portions of the gold compound.

Method for making patterned gold metallization

Substrate heating during sputter coating, due to charged particles, is controlled by the use of an auxiliary magnet in the vicinity of the substrate. The magnet is arranged to either increase this charge particle flux, in situations in which additional heating is desired, or reducing this charge particle flux in situations in which heating is detrimental (e.g., the sputter coating of heat sensitive substrates such as polymer films).

Sputter coating with charged particle flux control

A method is disclosed for making precisely patterned platinum films in the manufacture of integrated circuit devices. The method calls for the deposition of a film of a platinum compound, whose heat of formation is in the range of from -100 to +10 Kcal/mole, patterning the film, and thermally reducing the patterned film to platinum metal.

Method for making patterned platinum metallization

The specification describes a procedure for multilevel metallization of semiconductor integrated circuits in which the severity of the step formed by the edges of the first level pattern and the intermediate insulator over which the second level metallization pattern extends is reduced by beveling the edge. The bevel occurs during selective etching of the first level metal as a consequence of depositing the first level metal over a range of diminishing temperatures. Metal layers, notably aluminum, deposited in this way exhibit a differential etch rate such that the layer etches more slowly as etching proceeds through the thickness of the layer. Bevels of the order of 30.degree. to the horizontal can be produced in this way.

Multilevel metallization for integrated circuits

High-resolution sputter etching of a relatively thick layer (of, for example, gold) by directly utilizing a relatively thin layer of resist as a sputter-etching mask is often not feasible. In such a case, it is known to use a sputter-etching mask made of an etch-resistant material such as titanium interposed between the resist and the relatively thick layer. In accordance with the invention, patterning of the titanium is achieved by a technique of sputter etching in a halocarbon atmosphere.

High-resolution sputter etching

In high resolution lithography, resolution impairment sometimes occurs due to dust collecting on the mask. The dust is often attracted to the mask by static electricity. The solution proposed is to coat the entire photomask with a transparent, electrically conductive coating. The coating is electrically grounded to drain static charge. Conductive materials are often used for lithographic masks, but the patterns cannot be grounded effectively because there are island regions in the pattern. If the pattern is itself conducting, there is the added option of applying the antistatic layer under the pattern. If the pattern is formed of a photographic emulsion of a patterned photoresist, it is protected from damage and wear in handling by the harder conductive coating.

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Berkeley Heights, NJ, United States of America

David B Fraser