Intel Corporation

Other

David B Fraser

Chien Chiang

Brian S Doyle

Gang Bai

Peng Cheng

Chuanbin Pan

Sychyi Fang

Vicky M Ochoa

Chunlin Liang

Quat T Vu

Robert S Chau

Donald S Gardner

Venkatesan Murali

Kenneth C Cadien

Leopoldo D Yau

Xiao-Chun Mu

Gary William Ray

Kevin M Connolly

Stephen Bradford Gospe

Jack S Uppal

Gopal Raghavan

Joyce C Sum

Jeremy A Theil

Ian A Young

Jin Hyung Lee

Thomas N Marieb

Eng T Gaw

M Lawrence Dass

Sing-Mo Tzeng

Sing-Mo H Tzeng

Chin-Shih Wei

Srinivasan Sivaram

Anne S Mack

Thomas N D Marieb

Chih-Shih Wei

An apparatus on a wafer, comprising; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising; one or more base frames, a fourth metal layer of the wall comprising; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising; one or more top frames each over the pass-thru; and a metal lid.

Shielded structures to protect semiconductor devices

A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

High dielectric constant metal oxide gate dielectrics

An interconnect structure for microelectronic devices indudes a plurality of patterned, spaced apart, substantially co-planar, conductive lines, a first portion of the plurality of conductive lines having a first Intralayer dielectric of a first dielectric constant therebetween, and a second portion of the plurality of conductive lines having a second intralayer dielectric of a second dielectric constant therebetween. By providing in-plane selectability of dielectric constant, in-plane decoupling capacitance, as between power supply nodes, can be increased, while in-plane parasitic capacitance between signal lines can be reduced.

In-plane on-chip decoupling capacitors and method for making same

An apparatus on a wafer, comprising: a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising: one or more base frames, a fourth metal layer of the wall comprising: one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising: one or more top frames each over the pass-thru; and a metal lid.

Method of creating shielded structures to protect semiconductor devices

A method for electrically coupling a first set of electrically conductive pads on a first semiconductor substrate to a second set of electrically conductive pads on a second semiconductor substrate is described. Dielectric material of a first thickness is deposited on at least one set of the first and second sets of electrically conductive pads. The first and second semiconductor substrates are then attached together such that such that the first and second sets of pads are substantially aligned parallel to one another and such that the dielectric material is disposed between the first and second sets of electrically conductive pads.

Method for capacitively coupling electronic devices

An interconnect structure for microelectronic devices includes a plurality of patterned, spaced apart, substantially co-planar, conductive lines, a first portion of the plurality of conductive lines having a first intralayer dielectric of a first dielectric constant therebetween, and a second portion of the plurality of conductive lines having a second intralayer dielectric of a second dielectric constant therebetween. By providing in-plane selectability of dielectric constant, in-plane decoupling capacitance, as between power supply nodes, can be increased, while in-plane parasitic capacitance between signal lines can be reduced.

A method of fabricating an image sensor having pin photodiodes residing vertically atop underlying CMOS control circuitry. In the preferred technique, pin photodiodes fabricated in amorphous silicon are utilized.

Method of fabricating image sensors using a thin film photodiode above active CMOS circuitry

An apparatus on a wafer, including; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall including; one or more base frames, a fourth metal layer of the wall including; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall including; one or more top frames each over the pass-thru; and a metal lid.

An image sensor having pin photodiodes residing vertically atop underlying CMOS control circuitry. In the preferred technique, pin photodiodes fabricated in amorphous silicon are utilized.

Image sensor using a thin film photodiode above active CMOS circuitry

A method and apparatus for capacitively coupling the input and output terminals of two semiconductor devices.

Apparatus for capacitively coupling electronic devices

The present invention relates to semiconductor devices. More specifically, the invention discloses the use of dummy structures to improve thermal conductivity, reduce dishing and strengthen layers formed with low dielectric constant materials.

Fabricating low K dielectric interconnect systems by using dummy structures to enhance process

A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.

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Danville, CA, United States of America

David B Fraser