International Business Machines Corporation

David B Eardley

Bernard A Denis

Harsaran S Bhatia

Richard Edward Matick

Santosh Prasad Gaur

Joseph R Cavaliere

Richard Thomas Dennison

Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP and one vertical NPN transistor in a merged structure. To obtain faster switching speeds, the PNP transistors are cross-coupled as flip-flop transistors while the NPN transistors act as load transistors. A word select signal is applied to forward bias the base-emitter junctions of the NPN load transistors, to thereby generate a potential difference between bit lines coupled to the emitters of the PNP flip-flop transistors.

Random access memory cell

A dynamic memory cell uses a low barrier Schottky contact at a drain region to eliminate the need for an external gating diode. The drain is separated from source and injector regions by a heavily doped N+ reach through region extending to a heavily doped N+ blanket semiconductor. Holes injected into one of the separated regions are trapped by high-low junctions and are detected by sensing the source-drain current.

Memory cell resistor device

A single shot multivibrator comprising two inverting OR circuits connected in closed loop configuration by a cascaded series of delay elements some of which are partially bypassed at selected locations so as to reduce the recovery time of the multivibrator. The delay elements comprise one or more inverting OR circuits positioned at the selected locations with the remainder being simple inverting circuits. Although the output pulse width of the multivibrator is determined by the total delay of the cascaded units, the recovery time is made a fraction thereof, depending upon the number and the locations of the bypasses.

Single shot multivibrator having reduced recovery time

Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP and one vertical NPN transistor in a merged structure. In a second embodiment, each bed contains one lateral PNP and two vertical NPN transistors in a merged structure. Memory access circuitry provides a high ratio of selected to unselected cell current in order to permit fast memory operation.

This matrix has high barrier Schottky diodes at Read or Reproduce Only Storage (ROS) matrix crossovers to represent 1's (the absence of diodes representing 0's) and low barrier Schottky diodes connected to select individual column lines (bit lines) of the ROS matrix. A current sink is connected to each column. Any unselected column causes the current in that column to be diverted through the respective low barrier diode, thus preventing that current from flowing into the selected word line. The only current that flows into the selected word line of a matrix depends from the single selected column current source.

Reproduce only storage matrix

A random access memory system is disclosed in which data stored in two distinct memory locations defined by distinct address signals can be non-destructively read out simultaneously. The system employs a matrix of two-port memory cells, each cell functioning to store one binary bit of data in a conventional cross-coupled common emitter flip-flop. A pair of input/output transistors have their emitters connected to the respective control nodes of the static cell, their bases connected to first and second word lines, and their collectors connected to first and second bit sense lines. The word lines and bit lines are addressed and pulsed such that during reading of the selected cells, current flows through only one of the input transistors of one of the cells of a sense line whereon, during writing, current flows through both of the input/output transistors, the direction of current flow during writing depending on the value of the binary bit being stored. The input/output transistors associated with each cell are integrated onto the chip and occupy only slightly more area than multi-configured devices conventionally employed in prior art two-port cells.

High speed high density, multi-port random access memory cell

A negative resistance circuit constructed of complementary field effect transistors has several applications. A voltage change at an input to the negative resistance circuit alters the current at the input node in a direction inverse to that normally caused by such a voltage change. The circuit can be used to speed up the charging or the discharging of a circuit node capacitance.

Delay circuits using negative resistance CMOS circuits

The disclosure is an improved Random Access Memory (RAM) integrated circuit chip. More specifically, enhancement - depletion mode field effect transistor technology is employed to provide a solid state memory having improved 'reading' and 'writing' capability. A pair of N-channel depletion mode devices are used to initialize the bit lines before the start of the next read or write cycle. These devices are switched to a high conductive state resulting in a rapid initialization of the bit lines. A sense latch circuit incorporating enhancement and depletion mode devices is used to detect and latch a small differential signal on the bit lines. The state of the sense latch is isolated from and does not affect the bit line voltages at any time during the memory cycle. M pairs of N-channel depletion mode devices are provided. One pair for each of B/S lines. M sense latch circuits are provided. One for each pair of B/S lines. In addition, there is provided a final sense latch circuit which is employed as the final latch in the bit circuits. The final sense latch is set with the data from a selected one of said M sense latch circuits. The final sense latch circuit provides an output which drives a data output driver.

Growing community of inventors

Stanfordville, NY, United States of America

David B Eardley