Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Skhynix Inc.

David B Carlton

Xin Guo

Aliasgar S Madraswala

Yogesh B Wakchaure

David J Pelster

Neelesh Vemula

Donia Sebastian

Mark Anthony Golez

Scott Nelson

Simon Ramage

Kai-Uwe Schmidt

Jonathan De Vries

Curtis A Gittens

Sarvesh Varakabe Gangadhar

Ryan J Norton

MarkAnthony Golez

Vivek Angoth

Ye Zhang

Ming Zhang

Sagar Upadhyay

Purval Shyam Sule

Jonathan M Hughes

Yu Du

Darshan Mallapur Vishwanath

Sagar S Sidhpura

Taehun Park

Wanik Cho

Gulzar Kathawala

Yushin Ahn

In accordance with some embodiments of the present disclosure, a method is performed by processing circuitry of a storage device for writing data to memory of a storage device. The method is related to executing a program to write data written in a plurality of single-layer cells (SLCs) in a first portion of the memory to a plurality of multi-level cells (MLCs) in a second portion of the memory using a single program command. The single program command includes an address of each SLC in the first portion of the memory and optionally, additional information regarding SLC read-level shifts. Executing the single program command includes reading from each SLC of the plurality of SLCs, storing at least some of the respective SLC data in the plurality of latches, and writing the SLC data that was stored in the plurality of latches to the plurality of MLCs.

Methods and systems for SLC copyback operations

An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, determine if a current workload for a particular NAND device of the plurality of NAND devices is a random write workload, and, if so determined, disable a program suspend operation for only the particular NAND device. Other embodiments are disclosed and claimed.

Dynamic program suspend disable for random write SSD workload

Mechanisms (which can include systems, methods, and media) for reducing power consumption of multi-plane non-volatile-memory (MPNVM) solid-states drives (SSDs) are provided. The mechanisms include: identifying a first MPNVM device and a first plane of the first MPNVM device associated with a first command; determining that one or more other commands are available for the first MPNVM device and for a plane of the first MPNVM device different from the first plane; and in response to determining that the one or more other commands are available for the first MPNVM device and for a plane of the first MPNVM device different from the first plane, sending the first command and the one or more other commands to the first MPNVM device for execution.

Systems, methods, and media for reducing power consumption of multi-plane non-volatile memory solid-state drives

A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Solid state drive with multiplexed internal channel access during program data transfers

A device and related method, the device including memory and processing circuitry. The memory includes sets of source memory bands and a defragmentation destination memory band. Each set of source memory bands includes source memory bands and at least one portion of each source memory band stores valid data. The processing circuitry determines a merit score corresponding to each source memory band based on one or more characteristics of portions of data of each corresponding source memory band and determines, for each set of source memory bands, a respective source memory band that corresponds to a second-highest merit score. The processing circuitry identifies a set of source memory bands that includes a source memory band corresponding to a highest second-highest merit score and stores at least one portion of valid data from the source memory bands of the identified set of source memory bands to the defragmentation destination memory band.

Devices and methods for improving multi-stream write amplification factor

A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

Method, system, and apparatus for multi-tiered progressive memory program operation suspend and resume

A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

Method, system, and apparatus for nested suspend and resume in a solid state drive

Provided are an apparatus, system and method for apparatus, system and method for throttling an acceptance rate for adding host Input/Output (I/O) commands to a buffer in a non-volatile memory storage device. Information is maintained on an input rate at which I/O commands are being added to the buffer and information is maintained on an output rate at which I/O commands are processed from the buffer to apply to execute against the non-volatile memory. A determination is made of a current level of available space in the buffer and an acceptance rate at which I/O commands are added to the buffer from the host system to process based on the input rate, the output rate, the current level of available space, and an available space threshold for the buffer to maintain the buffer at the available space threshold. I/O commands are added to the buffer to process based on the acceptance rate. The I/O commands are accessed from the buffer to process to execute against the non-volatile memory.

Apparatus, system and method for throttling a rate at which commands are accepted in a storage device

Embodiments include apparatuses, methods, and computer devices including a multi-level NAND memory array and a memory controller coupled to the multi-level NAND memory array. The multi-level NAND memory array may include a first word line and a second word line. The memory controller may receive a first page of data and a second page of data together with a program command to program the first page of data and the second page of data into the multi-level NAND memory array. The memory controller may program the first page of data into a page of the first word line via a first pass, and further program the second page of data into a page of the second word line via a second pass, subsequent to the first pass. Other embodiments may also be described and claimed.

Pseudo single pass NAND memory programming

In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.

Power management and monitoring for storage devices

Growing community of inventors

Oakland, CA, United States of America

David B Carlton