Advanced Micro Devices Corporation

David Ashby Steele

Khoi A Phan

Ramkumar Subramanian

Christopher Lee Pike

Jonathan Alan Orth

Yeng-Kaung Peng

Linda S Milor

Gurjeet S Bains

An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.

Method for reducing defects in a semiconductor lithographic process

A drip catching apparatus includes a trough 2 formed by a sidewall 26 and a drip catching surface 28 to prevent excess drops of a photoresist developer solution from dripping onto a semiconductor wafer 8 in a photoresist development cup 4. One or more holes 30 may be provided to drain the photoresist developer solution received by the drip trough 2.

Drip catching apparatus for receiving excess photoresist developer

Defects in integrated circuit wafers (10) are often difficult to diagnose, because patterned wafer inspections can only be done after certain wafer processing steps. Defect simulation is used to understand the relation between defects in the wafer (10) and the resulting wafer profiles. Defects such as particles (50) and bubbles (22) in the photoresist (28), for example, translate into a wide variety of defective profiles. Knowledge of the relation between defects and the defect profiles can assist in yield improvement efforts, since defects may be diagnosed by comparing simulated and observed defect profiles. From the simulated defect profiles, methods can be adapted to fix or correct observed defects.

Defect diagnosis using simulation for IC yield improvement

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Sunnyvale, CA, United States of America

David Ashby Steele