Mill Computing, Inc.

Other

Mathon Systems, Inc.

Mil Computing, Inc.

David Arthur Yost

Roger Rawson Godard

Arthur David Kahlich

John D Mathon

Rick Kiessig

Sebastien Paul Maurice Mirolo

Nachum M Kanovsky

A computer system provides at least one workspace as a user interface corresponding to a user-generated topic. A home topic is provided to the user as an initially selected topic. The home topic provides a workspace to the user as a user interface. User selection of a first topic within the home topic causes designation of the first topic as the current topic. A first workspace is associated with the first topic, and a first topic data structure associated with the first topic is generated and the first topic data structure is associated only with application windows, files and application related data used by the user while the first topic is designated as the current topic. The user is provided, within the first workspace, only application windows, files and application related data used by the user while the first topic is designated as the current topic.

Computer system with a plurality of work environments where each work environment affords one or more workspaces

A computer processor is provided that employs a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements as well as at least one functional unit that performs operations that produce and access the unitary operand data elements stored in the plurality of operand storage elements. The meta-data associated with a given operand data value as part of a unitary operand data element can specify type of the unitary operand data element (e.g., vector or scalar), elemental width and floating-point error flags. The meta-data can also be used to define special operand data values (e.g., Not-a-Result and None). The meta-data is useful in optimizing execution, such as in speculation and vectorized SIMD operations. The computer processor can also support a number of particular vector operations that are useful in optimizing execution of vectorized SIMD operations.

Computer processor employing operand data with associated meta-data

A computer system executes a spreadsheet application that accepts inputs from a user into a second cell of the spreadsheet document to reproduce a formula existing in a first cell of the spreadsheet. The formula references a first set for reference cells comprising one or more other cells in the spreadsheet document. Each of the one or more other cells in the spreadsheet document is positioned a relative distance from the first cell. The spreadsheet application reproduces the formula in the second cell while maintaining a link to cause any update of the formula in the first cell to be reflected in the second cell, and updates the formula in the second cell to generate a second set of reference cells wherein each cell in the second set of reference cells has a relative distance to the second cell that is equal to the relative distance of a corresponding cell in the first set of reference cells with respect to the first cell.

Computer system that can make a first spreadsheet cell behave similarly to a second cell by indirection through a 'ditto' function

A computer processor including an instruction buffer configured to store at least one variable-length instruction having a bit bundle bounded by a head end and a tail end with a plurality of slots each defining a corresponding operation, wherein the plurality of slots and corresponding operations are logically partitioned into a plurality of distinct blocks with a first group of blocks extending from the head end of the bit bundle toward the tail end of the bit bundle and a second group of blocks extending from the tail end of the bit bundle toward the head end of the bit bundle, wherein the second group of blocks includes a tail end block disposed adjacent the tail end of the bit bundle. A decode stage is operably coupled to the instruction buffer and configured to process a given variable-length instruction stored by the instruction buffer by decoding at least one operation of a particular block belonging to the first group of blocks in parallel with decoding at least one operation of the tail end block. Additional aspects are described and claimed.

Computer processor employing double-ended instruction decoding

A computer processor includes execution logic (having a number of functional units) configured to perform operations that access operand data values stored in a plurality of operand storage elements. Such operand data values include a predefined None operand data value indicative of a missing operand value. The operations include a RETIRE operation specifying a number of operand data values that is intended to be retired in a predefined machine cycle. During execution of the RETIRE operation, zero or more at None operand data values are selectively retired in the predefined machine cycle based on the number of operand data values specified by the RETIRE operation and the number of operand data values to be retired as a result of execution of other operations by the execution logic in the predefined machine cycle. Other aspects and software tools are also described and claimed.

Computer processor employing explicit operations that support execution of software pipelined loops and a compiler that utilizes such operations for scheduling software pipelined loops

A computer processor that operates on distinct first and second instruction streams that have a predefined timed semantic relationship. At least one of the first and second instruction streams includes variable-length instructions having a header and associated bundle bounded by a head end and a tail end. An alignment hole within the bundle encodes information representing at least one nop operation. The computer processor includes first and second multi-stage instruction processing components configured to process in parallel the first and second instruction streams. At least one of the first and second multi-stage instruction processing components includes an instruction buffer operably coupled to a decode stage. The decode stage is configured to process a variable-length instruction by isolating and interpreting the alignment hole of the variable length instruction in order to initiate zero or more nop operations that follow the timed semantic relationship between the first and second instruction streams.

Computer processor employing instructions with elided nop operations

A computer processor including a first memory structure that operates over multiple cycles to temporarily store operands referenced by at least one instruction. A plurality of functional units performs operations that produce and access operands stored in the first memory structure. A second memory structure is provided, separate from the first memory structure. The second memory structure is configured as a dedicated memory for storage of operands copied from the first memory structure. The second memory structure is organized with a byte-addressable memory space and each operand stored in the second memory structure is accessed by a given byte address into the byte-addressable memory space.

Computer processor employing byte-addressable dedicated memory for operand storage

A computer processor including a plurality of functional units that performs operations that produce result operands at different characteristic latencies over multiple cycles. An interconnect network provides data paths for transfer of operand data between functional units. The interconnect network includes first and second crossbar parts. The first crossbar part is configured to route result operands produced with the lowest characteristic latency to any other functional unit. The second crossbar part is configured to route result operands with higher characteristic latency relative to the lowest characteristic latency to the first crossbar part where such result operands are in turn routed to any functional unit. In another aspect, the functional units can be organized as multiple slots where each slot can produce multiple result operands of different characteristic latencies in the same cycle, and wherein each slot employs separate result registers for each characteristic latency present on the slot.

Computer processor employing split crossbar circuit for operand routing and slot-based organization of functional units

A computer processor and corresponding method of operation employs execution logic that includes at least one functional unit and operand storage that stores data that is produced and consumed by the at least one functional unit. The at least one functional unit is configured to execute a deferred operation whose execution produces result data. The execution logic further includes a retire station that is configured to store and retire the result data of the deferred operation in order to store such result data in the operand storage, wherein the retire of such result data occurs at a machine cycle following issue of the deferred operation as controlled by statically-assigned parameter data included in the encoding of the deferred operation.

Computer processor with deferred operations

During unfavorable network conditions, a system provides a fallback mode that ensures conversation intelligibility and eliminates dropouts. In the fallback mode, the system uses data retransmission and mitigates retransmission delay by breaking input and output audio into segments for flow control and by involving the users in flow control. On the receive end, when necessary, the system pauses audio output and indicates the pause to the receiving user to inform the receiving user that the pause is a system artifact rather than silence from the transmitting user. On the transmit end, when necessary to avoid accumulation of excessive end-to-end delay, the system suspends audio input and indicates the suspension to the transmitting user to inform the transmitting user that audio input is temporarily being ignored. The transmit end of the system decides when to suspend audio input based on current end-to-end delay, which is continually communicated from the receive end.

System for intelligible audio conversation over unreliable digital transmission media

A computer processor is operably coupled to a memory system. The memory system is configured to store instruction blocks, wherein each instruction block is associated with an entry address and multiple distinct instruction streams within the instruction block. The multiple distinct instruction streams include at least a first instruction stream and a second instruction stream. The first instruction stream has an instruction order that logically extends in a direction of increasing memory space relative to the entry address of the instruction block. The second instruction stream has an instruction order that logically extends in a direction of decreasing memory space relative to the entry address of the instruction block. The computer processor includes a number of multi-stage instruction processing components corresponding to the multiple distinct instruction streams within each instruction block. The number of multi-stage instruction processing components are configured to access and process in parallel instructions belonging to multiple distinct instruction streams of a particular instruction block stored in the memory system.

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Los Altos, CA, United States of America

David Arthur Yost