Hewlett-packard Development Company, L.p.

Compaq Information Technologies Group, L.p.

David Arthur James Webb, Jr

James B Keller

Derrick R Meyer

Richard Eugene Kessler

Steve Lang

Rahul Razdan

A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the message contains corrupted data. The processor then replaces the corrupted portion with a predetermined bit pattern known or otherwise programmed into all other processors in the system. The predetermined bit pattern indicates that the associated portion of data was corrupted. The processor that detects the error in the message preferably alerts the system that an error has been detected. The message now containing the predetermined bit pattern in place of the corrupted data is retransmitted to another processor. The predetermined bit pattern will indicate that an error in the message was detected by the previous processor. In response, the processor detecting the predetermined bit pattern preferably will not alert the system of the existence of an error. The same message with the predetermined bit pattern can be retransmitted to other processors which also will detect the presence of the predetermined bit pattern and in response not alert the system of the presence of an error. As such, because only the first processor to detect an error alerts the system of the error and because messages containing uncorrectable errors still are transmitted through the system, fault isolation is improved and the system is less likely to fall into a deadlock condition.

Special encoding of known bad data

A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (value) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.

Method and apparatus for determining availability of a queue to which a program step is issued out of program order

A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (valve) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.

Method and apparatus for determining availability of a queue which allows random insertion

An architecture which splits primary and secondary cache memory buses and maintains cache hierarchy consistency without performing an explicit invalidation of the secondary cache tag. Two explicit rules are used to determine the status of a block read from the primary cache. In particular, if any memory reference subset matches a block in the primary cache, the associated secondary cache block is ignored. Secondly, if any memory reference subset matches a block in the miss address file, the associated secondary cache block is ignored. Therefore, any further references which subset match the first reference are not allowed to proceed until the fill back to main memory has been completed and the associated miss address file entry has been retired. This ensures that no agent in the host processor or an external agent can illegally use the stale secondary cache data.

Method and apparatus for optimizing bcache tag performance by inferring bcache tag state from internal processor state

A technique handles load instructions within a data processor that includes a cache circuit having a data cache and a tag memory indicating valid entries within the data cache. The technique involves writing data to the data cache during a series of four processor cycles in response to a first load instruction. Additionally, the technique involves updating the tag memory and preventing reading of the tag memory in response to the first load instruction during a first processor cycle in the series of processor cycles. Furthermore, the technique involves reading tag information from the tag memory during a processor cycle of the series of four processor cycles following the first processor cycle in response to a second load instruction.

Methods and apparatus for processing load instructions in the presence of RAM array and data bus conflicts

A bypass mechanism is disclosed for a computer system that executes load and store instructions out of order. The bypass mechanism compares the address of each issuing load instruction with a set of recent store instructions that have not yet updated memory. A match of the recent stores provides the load data instead of having to retrieve the data from memory. A store queue holds the recently issued stores. Each store queue entry and the issuing load includes a data size indicator. Subsequent to a data bypass, the data size indicator of the issuing load is compared against the data size indicator of the matching store queue entry. A trap is signaled when the data size indicator of the issuing load differs from the data size indicator of the matching store queue entry. The trap signal indicates that the data provided by the bypass mechanism was insufficient to satisfy the requirements of the load instruction. The bypass mechanism also operates in cases in which multiple prior stores to the same address are pending when a load that needs to read that address issues.

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Groton, MA, United States of America

David Arthur James Webb, Jr