Lucent Technologies Inc.

Agere Systems Guardian Corp.

David Anthony Muller

Gregory L Timp

Glen D Wilk

Hans-Joachim Ludwig Gossmann

Harold Yoonsung Hwang

Paul H Citrin

Akira Ohtomo

A semiconductor device having composite dielectric layer formed between a silicon substrate and a gate electrode. The composite gate dielectric layer including a layer of silicon oxide, SiO, having a dielectric constant of greater than about 3.9 and about 12 or less, and a complementary dielectric layer for inhibiting the flow of leakage current through the composite dielectric layer.

Method of fabricating a composite gate dielectric layer

The present invention provides a semicondctor device that includes a conductor comprised of first and second layers of perovskite that have different stoichiometric compositions. The conductors provide a good template for the formation of dielectric layers thereon and are resistant to oxidizing environments used in semiconductor processing.

Oxidation-resistant conducting perovskites

A semiconductor device having a dielectric layer formed between a first and a second conductive layer. The dielectric layer comprising a layer of silicon oxide SiO, having a dielectric constant greater than about 3.9 and less than or equal to about 12.

Silicon oxide based gate dielectric layer

A semiconductor device having a dielectric layer formed between a first and a second conductive layer. The dielectric layer comprising a layer of silicon oxide, SiO , having a dielectric constant greater than about 3.9 and less than or equal to about 12.

We have discovered that, contrary to conventional wisdom about forming DP defects, electrical saturation in highly doped 2D layers of Si does not occur. In accordance with one aspect of our invention, free-carrier concentrations in excess of about 7&times;10 cm can be attained in single crystal Si layers &dgr;-doped with a Group V element. In one embodiment, free-carrier concentrations in excess of about 2&times;10 cm are realized in single crystal Si that is &dgr;-doped with Sb. In another embodiment, the &dgr;-doped layer is formed as an integral part of an FET. In accordance with another aspect of our invention, an integrated circuit is fabricated by the steps of providing a single crystal silicon body and forming a doped layer in the body, characterized in that the processing steps form neither a significant amount of electrically inactive precipitates nor a significant number of deactivating dopant centers containing vacancies, and the layer is fabricated as a &dgr;-doped layer that is doped with a Group V element, so that the free-carrier density in the layer is in excess of about 7&times;10 cm , preferably in excess of about 2&times;10 cm .

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Basking Ridge, NJ, United States of America

David Anthony Muller