Mie Fujitsu Semiconductor Limited

Qualcomm Incorporated

Broadcom Corporation

Suvolta, Inc.

United Semiconductor Japan Co., Ltd.

David Anthony Kidd

Lawrence T Clark

Augustine Kuo

Chao-Wu Chen

Vineet Agrawal

Matthew J Page

Paul Penzes

Edward John Boling

Sang-Soo Lee

Robert Rogenmoser

Samuel Leshner

Samy Shafik Tawfik Zaynoun

Michael S McGregor

George Tien

Rui Li

Venkat Narayanan

De Lu

Min Chen

Saravanan Marimuthu

Percy Tehmul Marfatia

Yi Lou

Ardavan Moassessi

Ramesh Senthinathan

Ankita Nayak

Peeyush Kumar Parkar

Nathan D Dias

Baldeo Sharan Sharma

Amit Patil

Paul Ivan Penzes

Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

Back end of line (BEOL) process corner sensing

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

Tipless transistors, short-tip transistors, and methods and circuits therefor

A ring oscillator is disclosed according to certain aspects of the present disclosure. The ring oscillator include N flip-flops, each of the N flip-flops having a data input, a clock input, and an output, wherein N is an integer greater than 1. In certain aspects, the output of each of the N flip-flops is coupled to the clock input of an adjacent other one of the N flip-flops, the output of each of the N flip-flops is coupled to a reset input or a preset input of a non-adjacent other one of the N flip-flops, and the data input of each of the N flip-flops is coupled to a voltage line or a ground line.

Sequential based ring oscillator

An integrated circuit (IC), including a substrate and back-end-of-line (BEOL) layers on the substrate is described. The IC includes a sensor in a BEOL layer (Mx) of the BEOL layers. The BEOL sensor includes conductive traces and shield traces interdigitated with the conductive traces in the BEOL layer Mx. The BEOL sensor also includes a first ground shield in a BEOL layer Mx&#x2212;1, and a second ground shield in a BEOL layer Mx+1. The BEOL sensor further includes logic configured to ground/float the shield traces.

Back-end-of-line (BEOL) on-chip sensor

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Integrated circuit device body bias circuits and methods

Techniques for power-density-based clock cell spacing and resulting integrated circuits (ICs) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and IR droop. With the power-usage density for each type of clock cell determined, the techniques assign a keep-out region for each type of clock cell that is not fixed for all types of clock cells. These regions are instead based on the heat and IR droop corresponding to estimated power-usage density for each type of clock cell. Clock cells are then placed in a layout of an IC. The resulting IC has clock cells spaced sufficiently to reduce heat and IR droop while concurrently having excellent timing closure and performance.

Power-density-based clock cell spacing

A flip-flop is provided that includes a master latch clocked according to a first delay during a normal mode of operation and clocked by a smaller second delay during a scan mode of operation.

High-speed flip-flop with robust scan-in path hold time

A method for modifying a design of an integrated circuit includes obtaining design layout data for the integrated circuit and selecting at least one SRAM cell in the integrated circuit to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer. The method also includes extracting, from the design layout, NMOS active area patterns and PMOS active area patterns associated with the SRAM cell to define an EBE NMOS active area layout and a EBE PMOS active area layout. The method further includes adjusting the EBE NMOS active area layout to reduce a width of at least pull-down devices in the SRAM cell and altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.

SRAM cell layout structure and devices therefrom

An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

Slew based process and bias monitors and related methods

An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.

Integrated circuit process and bias monitors and related methods

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San Jose, CA, United States of America

David Anthony Kidd