Xilinx, Inc.

David Andrews

David I Lawrie

Colin Stirling

In one embodiment, a method of block decoding is provided. For each of a plurality of data blocks input to a memory arrangement, a plurality of decoding iterations are performed using a circular pipeline of processing stages. For each decoding iteration, one processing stage of the circular pipeline performs a first set and a second set of soft-input-soft-output (SISO) decoding operations on a block of data. The first set of SISO decoding operations produces an intermediate block of data. The second set of SISO decoding operations is performed on the intermediate data block to complete the one decoding iteration. The next decoding iteration of the plurality of decoding iterations is performed using the next processing stage following the one processing stage of the circular pipeline of processing stages.

Pipelined turbo convolution code decoder

In one embodiment, a circular pipeline processing system is provided. The system includes a plurality of processing stages configured to operate in a circular pipeline. Each processing stage is configured to output a fully processed data block in response to completing a final processing iteration, and otherwise, store a partially processed data block in a memory buffer of the processing stage. Each processing stage is configured to select between an unprocessed data block and a partially processed data block from the memory buffer of a preceding processing stage, based on one or more of availability of memory sufficient for storage of an unprocessed data block or availability of a partially processed data block. The processing stage is configured to process the selected data block.

Circular pipeline processing system

A method for decoding an encoded message is described. The method includes obtaining a set of metrics which includes first and second state metrics, and first and second branch metrics. First and second offset values for the iteration are obtained. The first state and branch metrics are added together to obtain a first partial result. The second state and branch metrics are added together to obtain a second partial result. The second partial result is subtracted from the first partial result to obtain a difference. The first partial result and the first offset value are added together to obtain a first result. The second partial result and the second offset value are added together to obtain a second result. Either the first result or the second result is selected for output responsive to the difference. A log correction term is selected responsive to the difference.

Generating a log-likelihood ratio for signal processing

Method and apparatus for concatenated and interleaved turbo product code decoding are described. The turbo encoder include a plurality of decoders coupled to receive first portion of data, a processor coupled to receive second portion of the data, and a controller providing a plurality of control signals coupled to the plurality of decoders and the processor. A control signal of the plurality of control signals coupled to the processor when enabled configures the processor to pre-calculate the second portion of the data, where the second portion of the data is trellis termination data.

Method of and apparatus for implementing a decoder

Address generation by an integrated circuit is described. An aspect relates generally to an address generator which has first and second processing units. The second processing unit is coupled to receive a stage output from the first processing unit and configured to provide an address output. The stage output is in a first range, and the address output is in a second range. The first range is from &#x2212;K to &#x2212;1 for K a block size, and the second range is from 0 to K&#x2212;1.

Address generation

Simulation of noise and, more particularly, a coefficient generator for channel modeling, is described. A spectrum memory is for storing sets of constants for respective harmonics. At least one phase noise source is configured for generating phase noise. An Inverse Fourier Transform block is coupled to the spectrum memory and to the at least one phase noise source. The Inverse Fourier Transform block is configured to provide a read address to the spectrum memory for accessing at least one constant of a set of constants of the sets of constants from the spectrum memory and coupled to receive the phase noise from the at least one phase noise source.

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Falkirk, United Kingdom

David Andrews