Oasis Tooling, Inc.

Nvidia Corporation

David Andrew Chapman

Thomas Grebinski

Brian Roger Loiler

Eric Michael McSherry

An Nguyen

Eric Michael Lotter

Anthony Jose Morales, Jr

Embodiments of the present invention may be directed to an electronic connector. More specifically, the electronic connector may include a single connector body and a mounting end operable to couple the single connector body with an electronic board of an electronics unit. The electronic connector may also include a lower jack portion disposed in the single connector body and include multiple lower pin receptacles, where the lower jack portion is disposed adjacent to the mounting end and is operable to receive a first connector end of a first cable. The electronic connector may further include an upper jack portion disposed in the single connector body and include multiple upper pin receptacles, where the upper jack portion is disposed above the lower jack portion and is operable to receive a second connector end of a second cable.

Low-cost offset stacked power connector

One method implementation disclosed includes detecting matching leaf cells that are functionally identical (optionally, functionally similar) and assigning matching names for the matching leaf cells to replace original, non-matching names. Optionally, digests can be calculated for the leaf cells and used to detect similarities and/or differences. The matching names are propagated to at least some higher-level cells in the hierarchical design, in place of the original names. The method can further include calculating digests for at least some of the higher level cells after the propagating of the matching names into the higher level cells. Various design matching technologies can be used in combination with cell renaming and new name propagation, not limited to use of digests. Dependency chains can be calculated to improve propagation of names through the hierarchy.

Identifying hierarchical chip design intellectual property through digests

The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data. The similarities and differences of interest depend on the purpose of the granular analysis. The comparisons are useful in many ways.

Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow

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San Jose, CA, United States of America

David Andrew Chapman