Silicon Laboratories Inc.

Other

David Andreas

Timothy Thomas Rueger

William Hong

Jon C Dattorro

J William Mauchly

Albert J Charpentier

David P Bresemann

Robert C Wagner

Xun Yang

Christopher D Eckhoff

Richard D Loveman

In an exemplary embodiment, an apparatus includes a sensor integrated circuit (IC) that is adapted for ambient light sensing (ALS) and/or proximity detection. The sensor integrated circuit (IC) includes an integrated analog-to-digital converter (ADC) that is adapted to convert at least one signal related to ambient light sensing (ALS) and/or proximity detection to at least one digital signal, and an integrated light emitting diode (LED) driver that is adapted to drive at least one LED. The sensor IC also includes an integrated power management unit (PMU) that is adapted to reduce power dissipation of the sensor IC by running at a low duty cycle the integrated LED driver and the integrated ADC.

Apparatus with sensor functionality and power management and associated methods

Apparatus with optical functionality and power management and associated methods

In an exemplary embodiment, an apparatus includes a sensor integrated circuit (IC). The at least one integrated photodetector that is adapted to sense light, and an integrated analog-to-digital converter (ADC). The integrated analog-to-digital converter (ADC) is coupled to the at least one integrated photodetector, and is adapted to convert an output signal of one or more of the at least one integrated photodetector to one or more digital signals. The sensor integrated circuit (IC) further includes an integrated controller that is adapted to facilitate operation of the sensor integrated circuit (IC).

Apparatus with optical functionality and associated methods

A method includes the step of serially clocking a mask value through a plurality of subscriber line interface circuits (SLICs) until each SLIC stores a corresponding portion of the mask value, and serially communicating a command to the plurality of SLICs. Each SLIC responds to the command only if enabled by the corresponding portion of the mask value.

Serial device daisy chaining method and apparatus

Methods and apparatus associated with a plurality of serial devices designed to communicate with a bus master in either a daisy chain or a normal configuration are provided. One method includes the step of serially providing a command sequence having a channel identifier to a given device of a plurality of daisy chained devices. The channel identifier is modified as it passes thru each daisy chained device. A specific device is identified or enabled when the channel identifier it receives matches a pre-determined value.

A technique is provided for an electrical device to automatically detect one of a plurality of interface standards to operate in accordance with. More particularly, a direct access arrangement (DAA) for communicating with telephone lines is provided for utilization with modem communications over a phone line. The DAA may be configured to automatically detect and operate in accordance with a plurality of interface standards for communications to a host system. For example, the DAA may detect that communications are to be provided in accordance with the AC-97 interface standard or the Azalia interface standard. In one embodiment, a clock signal may be monitored to determine the proper interface mode. In another embodiment, the automatic detection of the proper interface mode may be accomplished by monitoring the data presented to the DAA through the interface standard.

Direct access arrangement (DAA) circuit having automatic interface identification

A method to enable unique identification of serial devices having a common bus for communication with a bus master includes the step of serially clocking a mask value through a plurality of serial devices until each serial device stores a corresponding portion of the mask value. Each serial device responds to a subsequent command only if enabled by the corresponding portion of the mask value. Another method includes the step of initializing a plurality of serial devices to one of a first mode and a second mode. If the plurality of devices are in the second mode, a mask value is serially clocked through the plurality of serial devices until each serial device stores a corresponding portion of the mask value. When in the first mode every serial device responds to a subsequent command. When in the second mode, only serial devices enabled by the corresponding portion of the mask value respond to the command. An apparatus includes a plurality of serial devices coupled to a bus master by a bus. The bus master clocks a mask value through the plurality of serial devices until each serial device stores a portion of the mask value. Each of the plurality of serial devices responds to a subsequent bus master issued command only if enabled by the corresponding portion of the mask value. In various embodiments, the plurality of serial devices may be a heterogeneous or homogeneous combination of devices. In one embodiment, at least one of the devices comprises a subscriber line interface circuit.

A digital signal processor for efficiently handling audio applications is disclosed. The single chip digital signal processor includes an on-chip instruction memory for outputting instructions representing an audio application program. Four busses, W, X, Y and Z, provide communication within the processor. An ALU performs a plurality of arithmetic and logical functions according to the instruction memory. Specialized implementations for functions have been specially developed for audio applications, for example, a single cycle average instruction, a jump on condition code instruction, a repeat instruction, a limit instruction. A Multiplier Accumulator/Barrel Shifter performs a plurality of MAC and shifting functions according to the instruction memory. The MAC/BS is coupled in parallel with the ALU and an Address Generator. The Address Generator performs a plurality of address calculation functions according to the instruction memory. Some of the data storage areas include: 1) a GPR memory for writing data to the X and Y busses and reading data from the Z bus; 2) an AOR memory for writing data to the W, X, and Y busses and reading data from the Z bus; and 3) an SPR memory for writing data to and reading data from the X, Y and Z busses and for outputting control information to the ALU, the MAC/BS and the AGEN.

Digital signal processor for audio applications

A single stage multi-rate finite impulse response filter is used as the decimating filter for a sigma-delta analog-to-digital converter. The filter uses 2048 22-bit coefficient values to produce a sampled data output signal having a sampling rate of 48 KHz and a sample resolution of 16 bits from an input signal having a sampling rate of 3.072 MHz and a sample resolution of one bit. The filter uses a single read-only memory to hold the 2048 coefficient values. The coefficient values are distributed to eight four-way multiplexed accumulators by a circuitry which includes a signal multiplexer and a barrel shifter. The accumulators use unsigned arithmetic to calculate the output sample values. A value C0, representing a normalizing offset and gain applied to each of the coefficient values, is selected such that 2048 times C0 is a value which overflows the accumulator, leaving a value of zero in the accumulator.

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Austin, TX, United States of America

David Andreas