Infineon Technologies Ag

International Business Machines Corporation

Samsung Electronics Co., Ltd.

David Alvarez

Cornelius Christian Russ

Wolfgang Soldner

Krzysztof Domanski

Christian Cornelius Russ

Jens Schneider

Gernot Langguth

Kiran V Chatty

Kai Esmark

Klaus Von Arnim

Adrien Benoit Ille

Manfred Eller

Uwe Paul Schroeder

Richard Lindsay

Martin Wendel

Stefan Seidl

Robert Gauthier

Krysztof Domanski

Bong Jae Kwon

Techniques for electrostatic discharge (ESD) protection that apply a negative voltage to an MOS power clamp during an ESD event. The power clamp may be initially turned on by a short positive pulse to the gate to trigger the power clamp to switch into a parasitic bipolar mode, to quickly shunt the electrical energy from the ESD event around other circuitry. However, repeatedly triggering an NMOS power clamp into bipolar mode may cause the power clamp performance to degrade. For example, the NMOS power clamp may develop an increase in leakage current. The techniques of this disclosure apply a negative voltage to the gate of the power clamp which may reduce the holding and triggering voltage during the ESD event as well as improve leakage degradation of the power clamp after repeated ESD events.

ESD power clamp with negative gate voltage

An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Diode biased ESD protection devices and methods

In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

Semiconductor ESD circuit and method

Diode biased ESD protection device and method

Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.

Electrostatic discharge clamping devices with tracing circuitry

Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.

Electrostatic discharge blocking circuits

ESD protection device and method

An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier.

Semiconductor ESD device and method

An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first edge of the gate, wherein the first source/drain region is doped with a dopant of a second conductivity type opposite the first conductivity type, and at least a portion of the first source/drain region is doped with a dopant of the first conductivity type. The concentration of the second conductivity type dopant exceeds the concentration of the first conductivity type dopant, and the concentration of the first conductivity type dopant in the first source/drain exceeds the first concentration. A second source/drain region is also formed at the upper surface of the semiconductor body adjacent to a second edge of the gate, wherein the second source/drain region is doped with a dopant of the second conductivity type.

Semiconductor ESD device and method of making same

Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node.

Electrostatic discharge protection circuit, integrated circuit and method of protecting circuitry from an electrostatic discharge voltage

Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one electrostatic discharge (ESD) protection circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.

Electrostatic discharge (ESD) protection circuit placement in semiconductor devices

A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.

Growing community of inventors

Munich, Germany

David Alvarez