University of Washington

David Allstot

Xiaoyong Li

Douglas Reed Beck

Parmoon Seddighrad

Jacques Christophe Rudell

Jeffrey Walling

Daibashish Gangopadhyay

Kiyong Choi

Sangmin Yoo

Disclosed herein are example methods, systems, and devices for compressed sensing analog to digital conversion. In an example embodiment, a multiplication circuit is configured to multiply an input signal with a measurement signal to produce a multiplied signal, where the measurement signal includes data from a column of a measurement matrix. The measurement matrix may be generated by a linear feedback shift register (LFSR)-based measurement-matrix generator. An integration circuit may be coupled to the multiplication circuit and configured to integrate the multiplied signal for a predefined amount of time to produce an integrated signal. An analog to digital converter (ADC) circuit may be coupled to the integration circuit and configured to (i) sample the integrated signal and (ii) produce an output signal comprising at least one sample of the integrated signal. A column-wise multiplication of the input signal with the measurement signal enables an efficient compressed-sensing analog-to-digital conversion architecture.

Methods and systems for compressed sensing analog to digital conversion

Disclosed herein is an improved power amplifier, referred to as a Switched-Capacitor Radio Frequency Power Amplification (SCPA). The SCPA may be fabricated with scale CMOS technology. The SCPA may include a plurality of stages, each stage including a storage device, a switch, and selection circuitry. Various combinations of the stages may produce an output signal based on characteristics of a reference signal to be amplified. The output from the stages may be combined to create an amplified approximate square wave. The amplified square wave may be filtered by output circuitry such as a bandpass matching circuit, resulting in an output signal that may be an amplified version of the reference signal.

All-digital switched-capacitor radio frequency power amplification

A harmonic-rejection power amplifier is disclosed. In an embodiment, the harmonic-rejection power amplifier includes a plurality of stages, each stage comprising a respective signal-generation component coupled to a respective power amplifier, wherein the respective signal-generation component is configured to output a respective signal having a respective phase, and wherein the respective power amplifier is configured to output an amplified version of the respective signal. In the harmonic-rejection power amplifier, each respective phase differs from each other respective phase by a respective amount that is predefined based on a number of stages in the plurality of stages, and the plurality of stages are coupled in parallel to a combiner configured to combine the output of each respective power amplifier into a combined output. At least one harmonic in the combined output may be at least partially rejected.

Harmonic-rejection power amplifier

Embodiments of the present invention include a common-gate amplifier having an input terminal and an output terminal, a transistor having a source, a drain, and a gate, four inductors, and two capacitors, and a negative amplification circuitry. The negative amplification circuitry has an input terminal to receive an RF signal. The negative amplification circuitry applies negative or zero amplification to the RF signal and outputs the negative or zero amplified signal on an output terminal. Alternative embodiments include a Colpitts differential oscillator, which includes two Colpitts single-ended oscillators. Each Colpitts single-ended oscillator includes a transistor. The source of the transistor in one Colpitts single-ended oscillator may be capacitively coupled to the gate of the transistor in the other Colpitts single-ended oscillator.

Receiver with colpitts differential oscillator, colpitts quadrature oscillator, and common-gate low noise amplifier

A differential RF non-linear power amplifier employing low-voltage transistors in a cascode configuration uses self-biasing solutions rather than external biasing techniques to overcome transistor breakdown problems. The self-biasing solution ensures that the cascode devices and driver device operate below breakdown voltage limitations. A low resistance circuit is placed in parallel with the self-biased circuitry to mitigate increased on-resistance created by the self-biasing solution. PMOS and NMOS inverter legs provide digital programming of the conduction angle for the power amplifier. Changing the PMOS and NMOS strengths in the chain of inverter legs changes the conduction angle.

Self-bias and digitally tunable conduction angle circuits for a differential RF non-linear power amplifier employing low-voltage transistors

Methods and apparatuses for double-sampling a signal using an operational amplifier having dedicated unswitched connections to sample and hold circuits. In one embodiment, a circuit according to the teachings of the present invention includes an op-amp having four input terminals. Two of the input terminals are tied to ground and the other two terminals are coupled to S/H circuits through unswitched connections. In one embodiment, the S/H circuits are coupled to sample an input signal during different clock phases.

Growing community of inventors

Seattle, WA, United States of America

David Allstot