Asuragen, Inc.

Agere Systems Inc.

Oracle International Corporation

Mirna Therapeutics, Inc.

Hewlett-packard Development Company, L.p.

Nxp Usa, Inc.

Intel Corporation

The Johns Hopkins University

Compaq Computer Corporation, Inc.

Tandem Computers Incorporated

Ambion, Inc.

Lsi Corporation

Applied Biosystems, LLC

Compaq Information Technologies Group, L.p.

Bioo Scientific Corporation

David Allen Brown

Kevin Kelnar

Eric Devroe

Lance Ford

Mike Byrom

Dmitriy Ovcharenko

Angie Cheng

Rich Jarvis

William P Bunton

Rishabh Jain

Jeffrey Shelton

David Sonnier

Erik Schlanger

Michael Alexander Duller

John C Krause

Emmanuel Labourier

Kerri Keiger

Jaclyn Shingara

Sam Idicula

William J Watson

David Joseph Hawkins

Michael Rohleder

Charles Edward Peet

Peter Anthony Campochiaro

Leslie Zsohar

Marianna M Goldrick

George Adrian Ciusleanu

Sean W McGee

Jikui Shen

Rick Conrad

Ivonne Moon

Patricia Powers

David J Garcia

Matthew M Winkler

Victor A Bennett

Amit Shah

Charles E Peet, Jr

Andreas Bader

Daniel Fowler

Christopher Joseph Daniels

Alex Adai

Marcus Mueller

David T Heron

Stephanie Volz

Randy L Findley

Gary D Thompson

Robert W Horst

Asif Khan

Melvin K Benedict

William G Burroughs

John Michael Brown

Deepak Mital

Brittan L Pasloske

William F Bruckert

Richard W Cutts, Jr

Mauricio Calle

James S Klecka

Roger Ned Bailey

Steven J Pollock

Joseph R Hasting

Richard A Jarvis

James Thomas Kirk

Chris Randall Stone

Hanan Z Moller

Jeffrey Freeman

Peter M Ippolito

Shannon E Lawson

Robert A Corley

Ashish Choudhary

Ilhan Hatirnaz

Carl W Kagy

Abraham Prasad

David P Sonner

Elizabeth Mambo

Tiffany Sanford

Vince Pallotta

Jason F Wiggins

Lubna Patrawala

A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.

Hardware for supporting OS driven observation and anticipation based on more granular, variable sized observation units

An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value. The first compare circuit is configured to assert a first match signal in response to detecting a match between the counter value and the first preload value. The second peripheral circuit is configured to send a first preload request to the first peripheral circuit in response to an assertion of the first match signal. The first preload request identifies the location where the first instructions of the first task can be found in the external memory.

Hardware for supporting time triggered load anticipation in the context of a real time OS

A power control system, method, and architecture are disclosed for a multi-bank memory which provides independent, concurrent memory access to at least one memory block in each memory bank by using observation circuits to monitor bus masters connected over bus master interface signals to an interconnect for memory access requests to the multi-bank memory and to provide notifications to a power control circuitry that a valid memory access request was issued by a bus master over the bus master interface, where the power control circuitry processes the notifications received from each observation circuit and generates therefrom power control signals that are provided directly to each memory block and to bypass the interconnect, thereby separately controlling a power state for each memory block with power-up control signals that arrive at each memory block at or before a memory access request sent over the interconnect.

High performance method for reduction of memory power consumption employing RAM retention mode control with low latency and maximum granularity

Techniques are provided for configuring and operating hardware to sustain real-time hashing throughput. In an embodiment, during a first set of clock cycles, a particular amount of data items of a first data column are transferred into multiple hash lanes. During a second set of clock cycles, the same particular amount of data items of a second data column are transferred into the hash lanes. The transferred data items of the first and second data columns are then processed to calculate a set of hash values. When combined with techniques such as pipelining and horizontal scaling, the loading, hashing, and other processing occur in real time at the full speed of the underlying data path. For example, hashing throughput may sustainably equal or exceed the throughput of main memory.

Dynamically configurable high performance database-aware hash engine

Hardware for supporting OS driven load anticipation based on variable sized load units

Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

Processor core to coprocessor interface with FIFO semantics

Techniques are provided for improving the performance of a constellation of coprocessors by hardware support for asynchronous events. In an embodiment, a coprocessor receives an event descriptor that identifies an event and a logic. The coprocessor processes the event descriptor to configure the coprocessor to detect whether the event has been received. Eventually a device, such as a CPU or another coprocessor, sends the event. The coprocessor detects that it has received the event. In response to detecting the event, the coprocessor performs the logic.

Multi-purpose events for notification and sequence control in multi-core processor systems

Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine. Tabular data is efficiently copied between internal memories of the data movement system via a copy ring that is coupled to the internal memories of the data movement system and/or is coupled to a data movement engine. Also, a data movement engine internally broadcasts data to other data movement engines, which then transfer the data to respective core processors. Partitioning may also be performed by the hardware of the data movement system. Techniques are used to partition data 'in flight'. The data movement system also generates a column of row identifiers (RIDs). A row identifier is a number treated as identifying a row or element's position within a column. Row identifiers each identifying a row in column are also generated.

Multicast copy ring for database direct memory access filtering engine

Tuple encoding aware direct memory access engine for scratchpad enabled multi-core processors

Row identification number generation in database direct memory access engine

Database tuple-encoding-aware data partitioning in a direct memory access engine

Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data. Based on the descriptor, the first set of electronic circuits determines control information indicating that the one or more data manipulation operations are to be performed on the tabular data and transmits the control information, using a hardware data channel, to a second set of electronic circuits to perform the one or more operations. Based on the control information, the second set of electronic circuits retrieve the tabular data from source memory location and apply the one or more data manipulation operations to generate the data manipulation result. The second set of electronic circuits cause the data manipulation result to be stored at the destination memory location.

Tuple encoding aware direct memory access engine for scratchpad enabled multicore processors

Run length encoding aware direct memory access filtering engine for scratchpad enabled multicore processors

The present invention concerns methods and compositions for isolating, enriching, and/or labeling miRNA molecules and for preparing and using arrays or other detection techniques for miRNA analysis. Moreover, the present invention concerns methods and compositions for generating miRNA profiles and employing such profiles for therapeutic, diagnostic, and prognostic applications.

Methods and compositions involving MicroRNA

Growing community of inventors

Austin, TX, United States of America

David Allen Brown