Cadence Design Systems, Inc.

Scimed Life Systems, Inc.

Google Inc.

Boston Scientific Corporation

Cardiovascular Imaging Systems, Inc.

Praesagus, Inc.

Reduction Technologies, Inc.

Boston Scientific Scimed, Inc.

Promed, Inc.

David Allan White

Taber H Smith

Vikas Mehrotra

Michael McSherry

Louis K Scheffer

William Martin Belef

Ed Fischer

Bruce Yanagida

Ronald J Jabba

Lawrence D Wasicek

W Martin Belef

Stephen M Salmon

Donald S Mamayek

Alfred E Williams

Eric Nequist

Yue-Teh Jang

Thomas C Moore

Eric Williams

Roland Ruehl

Veijo T Suorsa

Sagnik Nandy

Donald Masters

Keith Dennison

Prakash Gopalakrishnan

Rizza A Garcia

Martin Belef

Richard S Ginn

Wangyang Zhang

Elias Lee Fallon

Lik Mui

Regis R Colwell

Mathew Koshy

Akshat Shah

Richard A Bautista

Prakash Krishnan

Matthew Thompson

Hiram Chee

Veijo Soursa

Zhuo Li

Daniel M Lafontaine

Ivan Sepetka

Darin Charles Gittings

Jeffrey J Christian

Hongzhou Liu

Hui Sok Moon

Brian J Lowe

Jaydeep Yeshwant Kokate

Chao Cai

Bradley Frank Slaker

Thomas Andrew Newton

Eric M DoBrava

Andrew Mark Chapman

Hui Xu

Matthew Robert Jones

Hua Luo

Matthew A Liberty

Jonathan C Sell

John R McKenzie

Shang Li

Ashok Babu Amara

Jose A Martinez

Simon Wang

Joseph D Farrell

Weifu Li

Linda H Lammerts Van Bueren

Rizza Casasos

Ryan S Christian

Vance Kenzle

Rong Chang Yan

Kevin Damm

Lawrence Wasicek

William M Belef

The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more instances that need to be placed in the unplaced layout and the areas of the unplaced layout configured to receive the instances, wherein analyzing is based upon a row-based data structure. Embodiments may also include determining a location and an orientation for each of the one or more instances based upon the genetic algorithm and generating a placed layout based upon the determined location and orientation for each of the instances.

System, method, and computer program product for analog and mix-signal circuit placement

Methods, systems, and computer readable medium include receiving, from a user device, a request for a digital component, receiving a data set of user-provided information regarding a particular product design, generating, based on the data set, a visual representation mapping design factors to potential product design geometry, segmenting the visual representation based on the design factor values, selecting a segment that contains less than a threshold amount of data points, selecting a digital component, dynamically altering, based on the selected segment, a presentation of the digital component that solicits information from the user about the segment, distributing, for presentation at the user device, the dynamically-altered digital component, obtaining, from the user device through a feedback mechanism, feedback information regarding the segment that contains less than the threshold amount of data points, and modifying a design factor of the particular product design based, at least in part, on the feedback information.

Automatically and intelligently exploring design spaces

Methods, systems, and computer readable medium include receiving, from a user device, a request for a digital component, determining an attribute of the user based information provided by the user or information contained in the request, identifying a behavioral model corresponding to the attribute, dynamically altering a presentation of an item depicted by the digital component based on the identified behavioral model, determining that the user corresponds to an underrepresented segment of a user population in a database containing information about the item, and in response, generating a digital component that includes the dynamically altered presentation of the item, solicits feedback from the user regarding the item, and includes a feedback mechanism, updating the database to include the feedback obtained, and modifying presentation of the item when distributed to other users having the attribute of the user based, at least in part, on the feedback obtained.

Automatically improving data quality

The present disclosure relates to embodiments for collaborative electronic design. Embodiments may include receiving a baseline model at a computing device associated with each of a plurality of geographically dispersed electronic design teams. Embodiments may further include applying environmental data from each of the plurality of geographically dispersed electronic design teams to the baseline model. Embodiments may also include generating a plurality of training changes, based upon, at least in part, the applied environmental data from each of the plurality of geographically dispersed electronic design teams. Embodiments may also include encrypting the plurality of training changes to create a plurality of encrypted training changes. Embodiments may further include providing the plurality of encrypted training changes to a centralized host configured to aggregate the plurality of encrypted training changes.

System, method, and computer program product for distributed learning in an electronic design

Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points, and the initial movement is expanded to consider additional placement options for the clock gate based on the data path connection points.

Clock gate placement with data path awareness

Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations.

Method and system for automatically extracting layout design patterns for custom layout design reuse through interactive recommendations

The present disclosure relates to a system and method for electronic design recommendations. Embodiments may include receiving, using at least one processor, an electronic design. Embodiments may further include recognizing one or more circuits within the electronic circuit design. Embodiments may also include identifying one or more user-specific circuit performance preferences. Embodiments may further include generating a first set of one or more placement and routing topology recommendations based upon, at least in part, the one or more user-specific circuit performance preferences. Embodiments may also include receiving a selection of at least one of the placement and routing topology recommendations. Embodiments may further include generating a second set of one or more placement and routing topology recommendations based upon, at least in part, the selected at least one placement and routing topology recommendations.

System and method for recommending integrated circuit placement and routing options

Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the EM related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.

Methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness

Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.

Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness

A device for occluding body lumens such as fallopian tubes which has an occluder element which has a lumen and a fixation element located in the lumen of the occluder element. The fixation element has at least one looped wire which has a proximal region which is biased radially outwardly and be constrained prior to deployment of the device.

Fallopian tube occlusion devices and methods

The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products.

Robust design using manufacturability models

Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation.

Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness

Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks.

Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs

Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied. Some embodiments further map schematic level parasitic constraints to a physical design representation and then compares the mapped parasitic constraints with corresponding electrical constraints to determine whether the mapped constraints are met.

Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness

Disclosed are a method, system, and computer program product for implementing electronic circuit designs with IR-drop awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to IR-drop analysis on the component, and determines whether the component meets IR-drop related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the IR-drop related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.

Methods, systems, and articles of manufactures for implementing electronic circuit designs with IR-drop awareness

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San Jose, CA, United States of America

David Allan White