Texas Instruments Corporation

David Alexander Grant

Dale J Skelton

Taylor R Efland

Chin-Yu Tsai

David D Briggs

Ramanathan Ramani

Robert Martinez

Ayesha I Mayhugh

Vadim Valerievich Ivanov

David John Baldwin

Roy Alan Hastings

Brian Ashley Carpenter

Kenneth George MacLean

Wayne Tien-Feng Chen

Larry J Wofford

Jin Liang

David G Daniels

Dolly Y Wu

Ben A Dowlat

Alan Johnson

Louis Albert Williams, Iii

Cormac Harrington

John C Teel

Andrew Alleman

Ken Moushegian

Laura A Hnilo

Garry Trevor Tomlins

David L Skinner

Hagen Wegner

Mike P Pierce

Dolly T Wu

Oscillation frequency measurements for trimming oscillators on an integrated circuit device are performed entirely on the device. The oscillation frequency measurements utilize a reference clock. Some measurements count periods of the oscillator signal independently of the reference clock, and some measurements count periods of the reference clock independently of the oscillator signal. After one oscillator on the device has been trimmed, that trimmed oscillator may then be used to make oscillation frequency measurements for trimming another oscillator on the device.

Fast on-chip oscillator trimming

A non-volatile memory, such as a one-time programmable memory, with a dual purpose read/write cache. The read/write cache is used as a write cache during programming, and stores the data to be written for a full row of the memory array. The programming operation simultaneously programs all cells in the selected row based on the contents of the write cache. In subsequent read operations, the read/write cache is used as a read cache. A full row of the array is simultaneously read in a read access, and the contents of that row are stored in the read cache. Subsequent access to that same row causes the data to be read from the read cache rather than requiring access of the array.

Dual-function read/write cache for programmable non-volatile memory

Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit.

Read margin measurement in a read-only memory

Communications systems and methods for transmitting communications between a charge system and an AC adapter are disclosed. In one embodiment, a communication system comprises an AC adapter disconnect switch that is switchable between coupling and decoupling an AC adapter DC output voltage to the charge system and a charge controller configured to modulate the AC adapter disconnect switch between coupling and decoupling to provide a communication signal to the AC adapter.

Communication systems and methods for transmitting communications between a charge system and an AC adapter

Oscillator circuitry having a switching inverting amplifier arranged in a ring oscillator configuration of at least two stages. A bias generator for supplying the amplifiers of neighboring stages, is responsive to an enable signal to supply the amplifiers only when the enable signal is asserted. A first pair of transistors, coupled to an input of one of the amplifiers and the other coupled to an output of the amplifier, the transistors being driven in common by the enable signal such that when the enable signal is deasserted the transistors of the pair are turned on to impose conflicting levels at the input and the output such that the amplifier is forced to switch.

Oscillators and clock generation

Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed example apparatus includes a reference level generator circuit to generate first and second reference signals and a bias signal based on a CMOS supply voltage, a source follower circuit to convert a CMOS input signal to a single-ended ECL signal based on the first and second reference signals, and an ECL buffer circuit to convert the single-ended ECL signal to a differential ECL output signal based on the bias signal and an ECL supply voltage.

Low-delay complimentary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus

Systems and methods are disclosed to enable determining thermal protection characteristics of an integrated circuit. In one embodiment, an integrated circuit includes a proportional to absolute temperature (PTAT) generator that provides a PTAT signal that varies as a function of temperature. Thermal protection control system provides an output signal indicative of a thermal protection condition based at least in part on the PTAT signal. A monitoring system that provides a path to enable selective measuring of at least one signal associated with operation of the thermal protection control system.

System and method for determining thermal shutdown characteristics

The present application describes a frequency compensation scheme for a linear voltage regulator circuit, or its special case, a low-drop out voltage regulator (LDO). According to one embodiment, the frequency compensation scheme includes two circuits, an inner loop compensation circuit (), and a circuit () at the output in parallel with one of the resistors of the output voltage divider (). These two compensation elements () are not interdependent and may be adjusted separately to provide more optimal frequency compensation. Advantages include smaller compensation circuit elements, die or board area savings, better phase margin over process technology variations and operating conditions, and ease of design adjustment.

Efficient frequency compensation for linear voltage regulators

Systems and methods are provided for detecting a state change of a level shifter and actively driving the level shifter into the new state to facilitate the recovery of the level shifter. The system and method also provide logic for setting up the level shifter for the next transition. A transition of a high logic to low logic of a first internal node and a second internal node is monitored. The first internal node and the second internal node transition between opposing logic levels, such that one internal node is pulled low and the other internal node is pulled high. The monitor determines when one node is pulled low and actively drives the other node to a logic high to facilitate the recovery of the level shifter.

Pulse response of fast level shifter

A switch mode converter uses the bootstrap capacitor to operate all the way to 100% duty cycle by adding only a very small amount of low-area extra circuitry. The additional circuitry includes a charge pump and a duty cycle detect device . When the duty cycle detect device detects that the converter is attempting to operate in % duty cycle, the charge pump provides additional charge to the bootstrap capacitor to ensure that the 100% duty cycle is maintained.

Switch mode converter that allows 100% duty cycle on gate driver

A power integrated circuit architecture ( ) having a high side transistor ( ) interposed between a control circuit ( ) and a low side transistor ( ) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region ( ) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring ( ) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays ( ) partitioned by at least one deep n-type region ( ), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

Line self protecting multiple output power IC architecture

An array ( ) of transistors ( ) formed in a p-type layer ( ), and including a second heavily doped p-type region ( ) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region ( ) is formed in the p-type layer ( ) and proximate a n-type buried layer ( ) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region ( ) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring ( ) collects the minority carriers (T ) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N well extending to the buried NBL layer. The guardring is preferably grounded when utilized as the low side transistor to collect minority carriers.

Growing community of inventors

Dallas, TX, United States of America

David Alexander Grant