Marvell Asia Pte., Ltd.

Cavium, Inc.

Cavium Networks, Inc.

Compaq Computer Corporation, Inc.

Other

David Albert Carlson

Richard Eugene Kessler

Shubhendu Sekhar Mukherjee

Michael S Bertone

Gregg Alan Bouchard

Muhammad Raghib Hussain

David Asher

Bradley D Dobbie

Isam Wadih Akkawi

Trent Parker

Wilson Parkhurst Snyder, Ii

David Kravitz

Manan Salvi

Srilatha Manne

Robert A Sanzone

Khaja E Ahmed

Michael D Varga

Vishnu V Yalala

Edward J McLellan

Thomas Frederick Hummel

Daniel Edward Dever

Thucydides Xanthopoulos

Amer Haider

Gerald Lampert

Steven W Aiken

Nitin Prakash

Curtis Miller

Rohit P Thakar

Anand Varadharajan

Derek S Brasili

Derek Scott Brasili

Wilson Snyder

A system and corresponding method unwind instructions in an out-of-order (OoO) processor. The system comprises a mapper. In response to a restart event causing at least one instruction to be unwound, the mapper restores a present integer mapper state and present floating-point (FP) mapper state, used for mapping instructions, to a former integer mapper state and former FP mapper state, respectively. The mapper stores integer snapshots and FP snapshots of the present integer and FP mapper state, respectively, to expedite restoration to the former integer and FP mapper state, respectively. Access to the FP snapshots is blocked, intermittently, as a function of at least one FP present indicator used by the mapper to record presence of FP registers used as destinations in the instructions. Blocking the access, intermittently, improves power efficiency of the OoO processor.

System and method for instruction unwinding in an out-of-order processor

In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.

Managing commit order for an external instruction relative to queued instructions

An instruction execution circuit operable to reduce two or more micro-operations into one by producing multiple permutation and merge results in one execution cycle. The execution circuit includes a permutation and merge switching fabric and a bank of multiplexers. For a fetched instruction, a decoder decodes an opcode to generate a set of control indications used to control the multiplexers to select bytes from the respective inputs that are destined for each of the multiple results. In this manner, multiple permutation results can be output from the execution circuits in one micro-operation.

Pair merge execution units for microinstructions

A circuit and corresponding method enable mining for digital currency in a blockchain network. The circuit comprises a controller and at least one partial hash engine that (i) implements a hash function, partially, to compute a partial hash digest of a final hash digest for a block header of a block candidate and (ii) generates a notification based on determining that the partial hash digest satisfies a criterion. The controller includes a complete hash engine that implements the hash function, completely. In response to the notification generated, the controller activates the complete hash engine to compute, in its entirety, the final hash digest for the block header, effectuating a decision for submission of the block candidate with the block header to the blockchain network for mining the digital currency. Power savings and reduction in area are achieved relative to multiple hash engines that compute the entire final hash digest.

System and method for mining digital currency in a blockchain network

A circuit and corresponding method enable bitcoin mining in a blockchain network. The circuit comprises a nonce generator that generates a nonce value, on a cycle-by-cycle basis, and changes only one binary digit of the nonce value per cycle. The circuit further comprises a hash engine that inserts, on the cycle-by-cycle basis, the nonce value into a block header of a block candidate and generates a digest by applying a hash function to the block header. The block header includes a representation of a target value. The circuit further comprises a validator that compares, on the cycle-by-cycle basis, the digest to the target value. In an event the digest satisfies the target value, the validator submits the block candidate to the blockchain network, causing newly minted bitcoin to be mined from the blockchain network. Changing only one binary digit of the nonce value, per cycle, reduces power consumption of the circuit.

System and method for bitcoin mining with reduced power

A system and corresponding method enforce strong load ordering in a processor. The system comprises an ordering ring that stores entries corresponding to in-flight memory instructions associated with a program order, scanning logic, and recovery logic. The scanning logic scans the ordering ring in response to execution or completion of a given load instruction of the in-flight memory instructions and detects an ordering violation in an event at least one entry of the entries indicates that a younger load instruction has completed and is associated with an invalidated cache line. In response to the ordering violation, the recovery logic allows the given load instruction to complete, flushes the younger load instruction, and restarts execution of the processor after the given load instruction in the program order, causing data returned by the given and younger load instructions to be returned consistent with execution according to the program order to satisfy strong load ordering.

System and method for implementing strong load ordering in a processor using a circular ordering ring

A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. This allows a user, who is interfacing with the hardware processor through software, to provide data of the datapath bit-width instead of the register bit-width. Advantageously, the user is agnostic to the size of the registers.

Implementing 128-bit SIMD operations on a 64-bit datapath

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Method and apparatus for managing global chip power on a multicore system on chip

A system and corresponding method map instructions in an out-of-order (OoO) processor. The system comprises a mapper, integer snapshot circuitry, and floating-point (FP) snapshot circuitry. The mapper maps instructions by mapping integer and FP architectural registers (ARs) of the instructions to integer and FP physical registers of the OoO processor, respectively. The mapper records, via at least one present FP indicator, presence of FP ARs used as destinations in the instructions. The mapper copies, periodically, the integer mapper state to the integer snapshot circuitry and copies, intermittently, based on the at least one FP present indicator, the FP mapper state to the FP snapshot circuitry. Copies of the integer and FP mapper state in the integer and FP snapshot circuitry, respectively, improve performance for instruction unwinding caused, for example, by an exception, branch/jump mispredict, etc. By copying the FP mapper state, intermittently, power efficiency of the OoO processor is improved.

System and method for instruction mapping in an out-of-order processor

A front-end portion of a pipeline includes a stage that speculatively issues at least some instructions out-of-order. A back-end portion of the pipeline includes one or more stages that access a processor memory system. In the front-end (back-end), execution of instructions is managed based on information available in the front-end (back-end). Managing execution of a first memory barrier instruction includes preventing speculative out-of-order issuance of store instructions. The back-end control circuitry provides information accessible to the front-end control circuitry indicating that one or more particular memory instructions have completed handling by the processor memory system. The front-end control circuitry identifies one or more load instructions that were issued before the first memory barrier instruction was issued and are ordered after the first memory barrier instruction, and causes at least one of the identified load instructions to be reissued after the first memory barrier instruction has been issued.

Managing load and store instructions for memory barrier handling

A merge unit configured to perform merge and permutation micro-operations by multiplexing data bytes of the inputs to simultaneously produce multiple data bytes of a merge and permutation result. Particularly, the merge unit includes a bank of MUXs arranged in parallel, each corresponding to one or more different data bytes in the merge result. When the merge unit is provided with a set of inputs, each MUX multiplexes the data bytes of the set of inputs (e.g., all the data bytes of the set of inputs) to selectively output a data byte to a particular location of the destination register storing the merge result. The selection by each MUX is individually controlled by a set of merge control words which identify a data byte location in an input and identify an input from the set of inputs.

Merge execution unit for microinstructions

Growing community of inventors

Haslet, TX, United States of America

David Albert Carlson