Linear Technology Corporation

National Semiconductor Corporation

Analog Devices International Unlimited Company

David Alan Pruitt

Frederick E Beville

Ramaswamy Ranganathan

Maurice O Othieno

John David Brazzle

Lothar Maier

William D Griffitts

A component-on-package circuit may include a component for an electrical circuit and a circuit module attached to the component. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides spring-like cushioning of force applied to the component in the direction of the circuit module.

Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits

A method of manufacturing integrated circuit (IC) devices includes the steps of providing a first frame that has openings each having a perimeter with shaped notches, placing a first die in at least one of the openings, and placing a second frame over the first frame. The second frame has a first partial dam bar with a first shaped tip that fits into a first shaped notch of the first frame. The method also includes the step of placing a third frame over the second frame. The third frame has a second partial dam bars with a second shaped tip that fits into a second shaped notch of the first frame. Each perimeter and the respective first and second partial dam bars cooperate to form a continuous dam completely encircling the die within the respective opening.

Stacked interposer leadframes

A stacked leadframe assembly is disclosed. The stacked leadframe assembly includes a first die having a surface that defines a mounting plane, a first leadframe stacked over and attached to the first die, a second die stacked over and attached to the first leadframe; and a second leadframe stacked over and attached to the second die. The leadframes have die paddles with extended side panels that have attachment surfaces in the mounting plane.

A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires. The wires, which preferably are made of copper, then may be bonded to the electrically conductive layer by melting the solder paste, preferably by heating the leadframe, allowing the solder to reflow and wet the wires, and then cool to produce a low resistance mass between the leads.

Flexible contactless wire bonding structure and methodology for semiconductor device

A semiconductor device is disclosed that has a die and a substrate having a die attachment area with a perimeter. A layer of solder connects the substrate and the die, the solder layer having at least one vent channel connected to the perimeter of the die attachment area, wherein the maximum distance from any point in the solder layer to the nearest free surface of the solder at a vent channel or at the perimeter of the die is less than the distance from the center of the die to the nearest edge of the die.

Enhanced pad design for solder attach devices

A packaging technique is described for QFNs, DFN, and other surface mount packages that allows the sides of leads to be plated with a wettable metal prior to the lead frames being singulated from the lead frame sheet. The leads of the lead frames in the sheet are shorted together and to the body of the lead frame sheet by a sacrificial interconnect structure. Chips are mounted to the lead frames and encapsulated, leaving the bottoms of the leads exposed. The lead frame sheet is then sawed along boundaries of the lead frames but not sawed through the interconnect structure. The sawing exposes at least a portion of the sides of the leads. The leads are then electroplated while the leads are biased with a bias voltage via the interconnect structure. After the plating, the lead frame sheet is sawed completely thorough the interconnect structure to singulate the lead frames and prevent the interconnect structure from shorting the leads together.

Lead plating technique for singulated IC packages

A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

Semiconductor device having a suspended isolating interconnect

A lead frame is configured for use with a singulation apparatus that eliminates flash. A die pad is attached to sides of the frame by tie bars and peripheral portions. The peripheral portions have cutout sections defining openings that are bridged by lead frame segments. The apparatus applies a downward force to the lead frame segments and translates the downward force to a horizontal force applied to the tie bars. The singulation process confines movement of the lead frame metal to within the plane of the lead frame.

Flashless lead frame with horizontal singulation

A leadframe is disclosed. The leadframe comprises a frame characterized by a substantially rectangular outline, a die paddle with a receiving surface, and a plurality of support members that connect the frame to the die paddle. The leadframe further comprises a plurality of leads connected to the frame, that will eventually serve to electrically connect an integrated circuit mounted on the die paddle to an external electrical device. The die paddle lies in a lower horizontal plane. A plurality of support members connect the frame with the die paddle. As projected on to a vertical plane that is perpendicular to the side of the frame to which a support member is attached, the offset angle between the support member and a vertical axis is less than 45 degrees.

Leadframe with support members

A lead frame for use in an integrated circuit package is herein disclosed wherein the lead frame is produced by molding an electrically conductive material into a desired lead frame shape. There is also disclosed several possible arrangements for a lead frame produced using the molding method including, protrusions on the lead frame adapted to provide a mechanical connection to the integrated circuit package, a heat sink molded as an integral part of the lead frame with heat dissipating characteristics specific to the application in which the lead frame will be used, and an arrangement which provides a heat conducting portion adapted to thermally connect a component attached to the lead frame to an external heat sink.

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San Jose, CA, United States of America

David Alan Pruitt