Mythic, Inc.

University of Michigan

Arm Limited

David Alan Fick

Skylar Skrzyniarz

Malav Parikh

Laura E Fick

Andrew Morten

Pei-Ci Wu

Sergio Schuler

Manar El-Chammas

Zainab Nasreen Zaidi

Bryant Sorensen

Raul Garibay

Vimal Reddy

Alex Dang-Tran

Paul Toth

Adam Caughron

David Theodore Blaauw

Scott C Johnson

Dennis Sylvester

Michael Henry

Erik Schlanger

Eric Stotzer

Balaji Iyer

Alexander Dang-Tran

Anthony Romano

John Mark Beardslee

Raul A Garibay, Jr

Michael B Henry

Evgeny Shapiro

Natarajan Seshan

Ilya Perminov

Michael Klachko

Daniel Graves

Scott Johnson

Matthew Rudolph Fojtik

Stuart David Biles

Trevor N Mudge

Scott McLean Hanson

Gregory Kengho Chen

Yoonmyung Lee

Bharan Giridhar

Michael John Wieckowski

Kaiyuan Yang

Michael Siegrist

Laura Fick

Ronald G Dreslinski

Michail Tzoufras

Skylar J Skrzyniarz

A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.

Systems and methods for implementing an intelligence processing computing architecture

Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Systems and methods for mapping matrix calculations to a matrix multiply accelerator

Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.

Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture

A system and method for enhancing inferential accuracy of an artificial neural network during training includes during a simulated training of an artificial neural network identifying channel feedback values of a plurality of distinct channels of a layer of the artificial neural network based on an input of a training batch; if the channel feedback values do not satisfy a channel signal range threshold, computing a channel equalization factor based on the channel feedback values; identifying a layer feedback value based on the input of the training batch; and if the layer feedback value does not satisfy a layer signal range threshold, identifying a composite scaling factor based on the layer feedback values; during a non-simulated training of the artificial neural network, providing training inputs of: the training batch; the composite scaling factor; the channel equalization factor; and training the artificial neural network based on the training inputs.

Systems and methods for enhancing inferential accuracy of an artificial neural network during training on a mixed-signal integrated circuit

A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.

Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture

Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.

System and methods for mixed-signal computing

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

A system and method for minimizing a total physical size of data buffers for executing an artificial neural network (ANN) on an integrated circuit includes implementing a buffer-sizing simulation based on sourcing a task graph of the ANN, wherein: (i) the task graph includes a plurality of distinct data buffers, wherein each of the plurality of distinct data buffers is assigned to at least one write operation and at least one read operation; (ii) the buffer-sizing simulation, when executed, computes an estimated physical size for each of a plurality of distinct data buffers for implementing the artificial neural network on a mixed-signal integrated circuit; and (iii) configuring the buffer-sizing simulation includes setting simulation parameters that include buffer-size minimization parameters and buffer data throughput optimization parameters; and generating an estimate of a physical size for each of the plurality of distinct data buffers based on the implementation of the buffer-sizing simulation.

Systems and methods for intelligent graph-based buffer sizing for a mixed-signal integrated circuit

A system and method for virtually addressing an array of accelerator tiles of a mixed-signal integrated circuit includes testing each of a plurality of distinct matrix multiply accelerator (MMA) tiles of a grid of MMA tiles, the grid of MMA tiles being defined by the plurality of distinct grid of MMA tiles being arranged in a plurality of rows and a plurality of columns along an integrated circuit, each of the plurality of distinct MMA tiles within the grid of MMA tiles having a distinct physical address on the integrated circuit; identifying one or more defective MMA tiles within the grid of MMA tiles based on the testing; and configuring the grid of MMA tiles with a plurality of virtual addresses for routing data to or routing data from one or more non-defective MMA tiles of grid of MMA tiles based on identifying the one or more defective MMA tiles.

Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture

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Ann Arbor, MI, United States of America

David Alan Fick