Stmicroelectronics Gmbh

Icera, Inc.

Hitachi, Ltd.

Other

Sgs-Thomson Microelectronics Limited

Somnium Technologies Limited

David Alan Edwards

Anthony Willis Rich

Andrew Michael Jones

Bernard Ramanadin

Stephen James Wright

Michael David May

Glenn Ashley Farrall

John A Carey

Margaret Rose Gearty

Joe Woodward

Atsushi Hasegawa

Anthony J Fitzpatrick

Jonathan Anthony Holmes

Alan Alexander

Martin Charles Young

The software development tool () forms part of a software development kit (). The software development tool () receives as input object files () and library files () and subjects the object file instructions and data definitions of the object files and the library files to re-sequencing to generate new object files and the links between them which are semantically equivalent to the input object files and library files and which are used to generate an optimized executable. The software development tool () is capable of automatically generating an executable, without requiring any modification of the source code, which is optimized to execute more deterministically and with respect to execution time; reduced processor and memory requirements; reduced off-chip memory accesses; reduced memory latency.

Software development tool to automatically generate an optimized executable

A method and processor for debugging a target processor. The method comprises: executing code on the target processor to generate trace information for debugging; and during execution of that code, periodically incrementing a value of a counter on the target processor. The execution of the code includes executing a plurality of timestamp instructions on the target processor each to associate a respective timestamp with the trace information. The execution of each timestamp instruction comprises generating the respective timestamp by reading the value of the counter into a software accessible storage location and subsequently resetting the counter.

Debugging system and method

Disclosed herein is a method of optimizing an executable program to improve instruction cache hit rate when executed on a processor. A method of predicting instruction cache behavior of an executable program is also disclosed. According to further aspects of the present invention, there is provided a software development tool product comprising code which when executed on a computer will perform the method of optimizing an executable program. A linker product and a computer program are also disclosed.

Instruction cache

The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.

Memory errors

The present invention provides a processor comprising: an execution unit arranged to execute a plurality of program threads, clock generating means for generating first and second clock signals, and storage means for storing at least one thread-specific clock-control bit. The execution unit is configured to execute a first one of the threads in dependence on the first clock signal and to execute a second one of the threads in dependence on the second clock signal. The clock generating means is operable to generate the second clock signal with the second frequency selectively differing from the first frequency in dependence on the at least one clock-control bit. A corresponding method and computer program product are also provided.

Clock control

An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

Interface for transferring debug information

A 'near wellbore modeling' software will, when executed by a processor of a computer, model a localized area of a reservoir field which surrounds and is located near a specific wellbore in the reservoir field by performing the following functions: (1) receive input data representative of a reservoir field containing a plurality of wellbores, (2) establish a boundary around one specific wellbore in the reservoir field which will be individually modeled and simulated, (3) impose an 'fine scale' unstructured grid inside the boundary consisting of a plurality of tetrahedrally shaped grid cells and further impose a fine scale structured grid about the perforated sections of the specific wellbore, (4) determine a plurality of fluxes/pressure values at the boundary, the fluxes/pressure values representing characteristics of the reservoir field located outside the boundary, (5) establish one or more properties for each tetrahedral cell of the unstructured grid and each cylindrical grid cell of the structured grid, (6) run a simulation, using the fluxes/pressure values at the boundary to mimic the reservoir field outside the boundary and using the fine scale grid inside the boundary, to thereby determine a plurality of simulation results corresponding, respectively, to the plurality of grid cells located inside the boundary, the plurality of simulation results being representative of a set of characteristics of the reservoir field located inside the boundary, (7) display the plurality of simulation results which characterize the reservoir field located inside the boundary, and (8) reintegrate by coarsening the grid inside the boundary, imposing a structured grid outside the boundary, and re-running a simulation of the entire reservoir field.

Near wellbore modeling method and apparatus

A circuit for monitoring information put onto an interconnect by one or more modules, said circuit comprising circuitry for determining if the information on the interconnect matches one or more conditions; and circuitry for preventing a module from putting further information onto said interconnect if it is determined that information on the interconnect matches said one or more conditions.

Circuit for monitoring information on an interconnect

In a system comprising an interconnect and a plurality of modules connected to said interconnect for putting information onto the interconnect, a circuit comprising circuitry for receiving at least part of said of said information; circuitry for determining if said at least part of said information satisfies one or more conditions; and circuitry for performing one or more actions in response to the determination that at least part of the information satisfies one or more conditions.

Detection of information on an interconnect

A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.

Method for compressing and decompressing trace information

Apparatus and method for shadowing processor information

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG-or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

Growing community of inventors

Bristol, United Kingdom

David Alan Edwards