Arm Limited

David Alan Boles

David Joseph Hawkins

Sandipkumar Ladhani

A memory device includes a memory array with first and second memory regions, multiple communication ports and coherency control circuitry. The communication ports couple the memory device to host computers, enabling a first host to write a data block to the second region, write a message, including a data descriptor of the data block, to the first or second region, and write message metadata, associated with the message, to the first region, and also to enable a second host to read the message metadata, the data descriptor and the associated data block. The coherency control circuitry controls coherency of data in the first region, including sending an invalidation request to the second host to invalidate a copy of the message metadata stored in a local cache of the second host. The invalidation request is sent in response to the first host writing the message metadata to the first region.

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Austin, TX, United States of America

David Alan Boles