Cadence Design Systems, Inc.

David Abada

Zhanhe Shi

Quang Nguyen

Pinchas Herman

Vu T Nguyen

Duc The Dang

Ty Doan

Subramanian Ganesan

Jinny Singh

Akash Sharma

Raju Joshi

Philip Henry Nils Anthony De Buren

A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.

Synchronized reset for a circuit emulator

A reconfigurable switching apparatus may include a plurality of communications transceivers operable to connect to a plurality of programmable integrated circuits. The reconfigurable switching apparatus may further include a plurality of crosspoint switches operably coupled to the plurality of communications transceivers. The reconfigurable switching apparatus may further include a processing circuitry operably coupled to the plurality of crosspoint switches and operable to program the plurality of crosspoint switches to route a plurality of interconnection paths between the plurality of communications transceivers.

Reconfigurable switch for a computing system

The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other logic that receive both a user clock as well as a fast global clock. With the disclosed transformations, the functionality of the original state element is maintained, and a single or low number of global clocks can be distributed in an FPGA of the prototype with user clocks generated locally on the FPGA.

Automatic clock to enable conversion for FPGA based prototyping systems

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San Jose, CA, United States of America

David Abada