Micron Technology Incorporated

David Aaron Palmer

Jonathan Scott Parry

Nadav Grosz

Deping He

Qing Liang

Christian M Gyllenskog

Stephen D Hanna

Kulachet Tanpairoj

Sean L Manion

Giuseppe Cariello

Reshmi Basu

Sushil Kumar

Sharath Chandra Ambula

Venkata Kiran Kumar Matturi

Sri Ramya Pinisetty

Luca Porzio

Lance W Dover

Yoav Weinberg

Fulvio Rori

Xinghui Duan

Massimo Zucchinali

A memory system may store temperature exception tracking in a temperature log, which may be separate from data to which the temperature information corresponds. A memory device may store data in a relatively higher-level cell and the corresponding temperature information in a relatively lower-level cell. To perform a write operation, the memory system may determine a current temperature at which the data is being written or was written to a partition of a memory device and may indicate in the temperature log if the current temperature is entering a temperature range that is outside a threshold temperature (e.g., a nominal temperature). To perform a read operation, the memory system may determine if the data to read was written to the memory device outside the threshold temperature to determine whether to perform temperature compensation for the read operation.

Temperature exception tracking in a temperature log for a memory system

Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Low-power boot-up for memory systems

In some implementations, a memory device may detect that data is to be written for a set of temperature profiles. The memory device may write, at respective temperatures corresponding to the set of temperature profiles, multiple copies of the data. The memory device may receive, from a host device, a read request associated with the data. The memory device may detect, based on receiving the read request, a current temperature of the memory device. The memory device may read a copy, from the multiple copies, that is associated with a temperature profile, from the set of temperature profiles, that corresponds to the current temperature of the memory device. The memory device may provide, to the host device, the copy of the data.

Thermal duplication of data

An apparatus can include a memory device and a controller coupled thereto. The controller can be configured to maintain a logical-to-physical (L2P) table including logical block addresses (LBAs). The LBAs are organized as partitions of the L2P table. Each partition of the L2P table includes a respective subset of the LBAs. The controller can be configured to monitor, for each partition of the LBA, a quantity of read/modify/write (R/M/W) operations and a quantity of read operations performed on the memory device at the respective subset of the LBAs. The controller can be configured to for each partition of the L2P table and based on the quantities of R/M/W operations and read operations performed on the memory device at the respective subset of the LBAs, adjust a value of respective granularities of the L2P table.

Adjustment to granularity of logical-to-physical table

Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.

Enhanced data reliability in multi-level memory cells

Methods, systems, and devices for techniques for improved write performance modes are described. A memory system and a host system may support a high performance mode to write data to the memory system. For example, the host system may provision a dedicated logical unit of the memory system. Upon detecting an urgent situation, the host system may transmit a command to the memory system to enter the high performance mode. In response to the command, the memory system may abort ongoing operations, such as internal memory management operations. Additionally, the host system and the memory system may configure operational parameters to increase the speed of write operations, such as a trim set for writing data to the logical unit, a bit rate of data transfer between the host system and the memory system, clock speeds of the memory system, or a combination thereof.

Techniques for improved write performance modes

Devices and techniques for enhanced flush transfer efficiency in a storage device are described herein. A flush trigger for a user data write can be identified. Here, user data corresponds to the user data write and was stored in a buffer. The size of the user data stored in the buffer is smaller than a write width for a storage device subject to the write. The difference ins the user data size in the buffer and the write width is buffer free space. Additional data can be marshalled in response to the identification of the flush trigger. Here, the additional data size is less than or equal to the buffer free space. The user data and the additional data can then be written to the storage device.

Write width aligned storage device buffer flush

A system includes a memory device associated with a logical address space, and a processing device, operatively coupled to the memory device. The processing device can provide, to a host system, usable capacity information and supported logical address granularity information for the logical address space. The processing device can obtain, from the host system, a logical address granularity configuration for a partition of the logical address space. The processing device can provide, to the host system, an acknowledgement of receipt of the logical address granularity configuration.

Logical address granularity configurations for logical address space partitions

Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.

Adaptive throughput monitoring

Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

Cache block budgeting techniques

Methods, systems, and devices for data alignment for logical to physical table compression are described. A controller coupled with the memory array may receive a command to access a logical block address associated with a memory device. In some cases, a first portion of a physical address of the memory device associated with the logical block address may be identified. The controller may perform an operation on the logical block address included in the command and identify a second portion of the physical address based on performing the operation. The physical address of the memory device may be accessed based on identifying the first portion and the second portion.

Page identification within a logical to physical table

The invention relates to a slide mechanism which can be attached to and support chair, couch or bed legs, one device per leg, to make furniture slidable. The chair, couch or bed leg fits an upward-facing leg holder for one furniture leg. The leg holder is affixed to or part of an upper base having two longitudinal grooves, wherein two screws, one extending into each of the grooves, hold the upper base to a lower base. The two screws are loose enough with respect to the upper side of the upper base to allow the upper base (carrying the leg-holder and the attached furniture leg) to slide relative to the lower base. An elastic member connects the upper base to the lower base.

Converter to make stationary furniture slidable or reciprocating

Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Sequential data optimized sub-regions in storage devices

Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Dynamic logical page sizes for memory devices

A system includes a memory device associated with a logical address space, and a processing device, operatively coupled to the memory device, to perform operations including providing, to a host system, power safety capability information for the logical address space, obtaining, from the host system, a power safety configuration for a partition of the logical address space, and providing, to the host system, an acknowledgement of receipt of the power safety configuration.

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Boise, ID, United States of America

David Aaron Palmer