Micron Technology Incorporated

Micron Display Technology, Inc.

David A Zimlich

David A Cathey

Glen Earl Hush

David H Wells

Garrett W Hall

Craig M Dunham

Tyler J Gomm

Thomas W Voshell

Manny K F Ma

Kip A Bedard

Manny K Ma

Kipp A Bedard

A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature.

Semiconductor temperature sensor using bandgap generator circuit

A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated circuit is disclosed. Such delay circuitry will inherently have a delay which is a function of temperature. Such temperature-dependent delays are compensated for by adjusting the power supply voltage of the VDL, delay element, or subcircuit. Specifically, a temperature sensing stage is used to sense the temperature of the integrated circuit. Information concerning the sensed temperature is sent to a regulator which derives the local power supply voltage from the master power supply voltage, Vcc, of the integrated circuit. If the temperature sensed is relatively high, the regulator increases the local power supply voltage, thus decreasing the delay and offsetting the increase in delay due to temperature.

Temperature compensation via power supply modification to produce a temperature-independent delay in an integrated circuit

A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated circuit is disclosed. Such delay circuitry will inherently have a delay which is a function of temperature. In accordance with embodiments of the invention, such temperature-dependent delays are compensated for by adjusting the power supply voltage of the VDL, delay element, or subcircuit. Specifically, a temperature sensing stage is used to sense the temperature of the integrated circuit, and hence the VDL, delay element, or subcircuit. Information concerning the sensed temperature is sent to a regulator which derives the local power supply voltage from the master power supply voltage, Vcc, of the integrated circuit. If the temperature sensed is relatively high, which otherwise would increase the delay though the VDL, delay element, or subcircuit, the regulator increases the local power supply voltage, thus decreasing the delay and offsetting the increase in delay due to temperature. Through this scheme, and assuming the temperature sensing stage is properly tuned, temperature-dependent delays can be reduced to approximately zero.

Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal

A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

Measure control delay and method having latching circuit integral with delay circuit

An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Access circuit and method for allowing external test voltage to be applied to isolated wells

A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.

Growing community of inventors

Boise, ID, United States of America

David A Zimlich