Bull Hn Information Systems, Inc.

Sequoia Systems, Inc.

Hutton/prc Technology Partners 1

Honeywell Information Systems Inc.

Honeywell Bull, Inc.

David A Wallace

Richard A Lemay

William E Woods

Jack J Stiffler

James M Nolan

Michael J Budwey

Richard A Karp

Kenneth J Izbicki

A priority resolver shortens the time between a requesting circuit initiating a request for access to a requested circuit that is shared with other circuits and the requesting circuit actually functioning with the requested circuit. A first portion of the priority resolver circuit is associated with the requesting circuit and makes a request for access to another portion of the priority resolver circuit associated with the requested circuit before the first portion has chosen the highest priority one of a plurality of requesting circuits that have concurrently bid for access to the requested circuit. Before the portion of the priority resolver associated with the requested circuit can respond to the access request and return an access grant signal, the first portion of the priority resolver circuit has chosen the highest priority requesting circuit. In this manner the time for accessing requested circuits is decreased.

Two-level priority arbiter generating a request to the second level

A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.

Multiple shared memory arrangement wherein multiple processors

A memory address controller addresses two memories and selectively modifies an address before it is applied to the addressing input of one of the two memories. A bit of the address is used to indicate to the controller if the address is to be modified. The same address is applied unchanged to the addressing input of the other of the two memories by the memory address controller. In this manner the addressing range is expanded.

Memory addressing arrangement

A memory bank selection arrangement has a memory which is made up of smaller memories each of which has a number of banks of memory. First bits of a memory address are used by an address controller for addressing a location in a selected bank of a first of the smaller memories. The address may be incremented by the controller before being used to address a second of the smaller memories, and a carry output is generated when the first bits are incremented and there is a carry from the highest order bit thereof. The memory address also includes second bits which are input to an adder which increments the number represented by the second bits responsive to the carry out from the controller to compensate for the incrementation of said first bits. The incremented or unincremented number output from the adder is used by a selector to select a bank of the smaller memories so that they can be addressed using the incremented or unincremented first bits.

Memory bank selection arrangement generating first bits identifying a

Memory failure detection apparatus is disclosed which is used with a large capacity memory that is organized in banks of memory, and with which error correction circuitry is used to correct correctable errors and provide an indication of same. The detection apparatus is responsive to the error indications and to a bank select addressing signal to provide and store error counts for a bank or banks of memory located on each memory board. A system processor periodically reads the error counts and responds to same to provide a maintenance message indicating that a specific memory board is to be replaced.

Memory failure detection apparatus

A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas. The transfer of the supervisor function from processor to processor is performed by registering the supervisor's identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors. Access to the common system bus by the processing elements is controlled by the associated interface units by means of a combination serial/parallel arbitration scheme which increases arbitration speed without requiring a full complement of request/grant leads.

Growing community of inventors

Chelmsford, MA, United States of America

David A Wallace