Texas Instruments Corporation

David A Thomas

Clive D Bittlestone

Francisco A Cano

John M Bach

Rand B Carawan

Hemant Joshi

A computer method of analyzing an integrated circuit ('IC') masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer that are suitable for milling, deleting portions of the target metal layer that do not meet minimum tool spacing requirements to produce a modified metal layer, deleting portions of the modified metal layer that do not meet minimum design rule width requirements to produce a final metal layer, and comparing the final metal layer and the cluster to identify common areas.

Determining feasibility of IC edits

A method of cross-mapping integrated circuit ('IC') elements nets in a IC and/or directing a probe to points on an IC to achieve minimal interference from adjacent structures is disclosed. The method of provides a more streamlined approach than referencing points from a physical layout representation of the IC to the actual IC being tested. The improved correlation between the actual packaged IC and the layout of the IC is accomplished using artificial locator cells. Preferably, the artificial locator cells are generated from mathematical operations of the extracted version of the layout, and they further provide coordinate information for where minimal interference from adjacent structures may be accomplished. Artificial locator cells may be generated from a layout representing a hierarchical representation or alternately each element that is instantiated from a reference library may already have artificial locator cells included.

Method of cross-mapping integrated circuit design formats

An integrated circuit has a power grid formed from a first set of power buses and on a metal interconnect level M a second set of power buses and on interconnect level M and a third set of power buses and on interconnect level M The set of power buses on level M are oriented in the same direction as the set of power buses on level M and both sets of buses are located coincidentally. A high power logic cell is pre-defined with a set of M -M power vias and so that logic cell can be positioned in a horizontal row unconstrained by pre-positioned M -M power vias. Dummy cell with M -M power vias is positioned as needed so as not to exceed a maximum strapping distance D A maximum value for distance D is selected based on dynamic power requirements of nearby logic cells as determined by simulation. A method for designing and fabricating integrated circuit is described.

Method for power routing and distribution in an integrated circuit with multiple interconnect layers

An integrated circuit,has a power grid formed from a first set of power buses,and,on a metal interconnect level M,, a second set of power buses,and,on interconnect level M,, and a third set of power buses,and,on inter-connect level M,. The set of power buses on level M,are oriented in the same direction as the set of power buses on level M,, and both sets of buses are located coincidentally. A high power logic cell,is pre-defined with a set of M,-M,power vias,and,so that logic cell,can be positioned in a horizontal row unconstrained by pre-positioned M,-M,power vias. Dummy cell,with M,-M,power vias is positioned as needed so as not to exceed a maximum strapping distance D,. A maximum value for distance D,is selected based on dynamic power requirements of nearby logic cells,as determined by simulation. A method for designing and fabricating integrated circuit,is described.

Optical systems for imaging activated pixels of a linear cantilever beam light valve (14) on a receptor or screen (24) are disclosed. The systems include a light source (12), a condenser lens (16) and pupil mask (26) forming a beam (32) from the output of the light source (12), a relay lens (18) for the beam (32) to image the pupil mask (26) onto the linear cantilever beam light valve (14), and an imaging lens (22) with an optional iris diaphragm (50) for imaging the portion of the beam (32) reflected from activated pixels of the light valve (14) onto the receptor or screen (24) while blocking the portion of the beam (32) reflected or diffracted from the remainder of the light valve (14).

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Sugar Land, TX, United States of America

David A Thomas