Texas Instruments Corporation

David A Tatman

Phat C Truong

John Frederic Schreck

Jozef C Mitros

Steven V Krentz

A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor () having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM () will breakdown during a programming operation by maintaining a breakdown voltage above a programming voltage. The breakdown voltage is, at least partially, increased by forming a p-doped region () within a semiconductor substrate (), and forming a drain region () of the OTP EPROM () within the p-doped region ().

One time programmable EPROM for advanced CMOS technology

The circuit and method of this invention provide for rapid and reliable detection of depleted or nearly-depleted cells in a column. The circuit is formed on the substrate of a nonvolatile, integrated-circuit memory including rows and columns of memory cells. The drain of each memory cell is connected to a drain-column line and the control gate that is connected to a wordline. One input of a sense amplifier is connected to the drain-column line. The other input of the sense amplifier is connected to a current reference formed on said substrate. The wordline is connected to a wordline test voltage and the output of the sense amplifier is coupled to an output pin of the integrated circuit. The current through the drain-column line is compared with the current through the current reference and, if the current through the drain-column line is sufficiently close to the current through said current reference, a signal is transmitted to an output pin of the integrated circuit.

Circuit and method for sensing depletion of memory cells

The indicator circuit and method of this invention include an OR circuit having at least two inputs and an output. A signature mode signal input is connected to one input of the OR circuit and a special test mode signal input is connected to a second input of the OR circuit. A logic circuit for providing indicator signals has at least three inputs and at least two outputs. A first input to the logic circuit is connected to the output of the OR circuit. At least one signature address signal is connected to a second input of the logic circuit. The signal indicating the results of the special test mode is connected to a third input of the logic circuit. A first preprogrammed code indicator circuit has an input connected to a first output of the logic circuit and a second preprogrammed code indicator has an input connected to a second output of the logic circuit. The first preprogrammed code indicator may contain, for example, a manufacturer code. The second preprogrammed code indicator may contain, for example, a device code.

Integrated circuit internal test mode indicator circuit

A test circuit for determining whether or not fuse-links of an integrated circuit have been opened or closed properly by, for example, a laser device. The test circuit of this invention, in one embodiment, includes a variable impedance, such as a P-channel transistor, connected between a voltage source and an output terminal, the impedance having one value with a first input applied to the variable impedance control terminal and having a second, larger value in response to a second input applied to the variable impedance control terminal. At least one programmable fuse-link and a gate are connected in series between the output terminal and a source of reference potential. A means for providing control inputs to the variable impedance is connected between a test mode input signal and the control terminal of the variable impedance. The means for providing control inputs to the P-channel transistor may include a second, current-mirror-connected P-channel transistor.

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Plano, TX, United States of America

David A Tatman