Apple Inc.

David A Stronks

Hopil Bae

Ahmad Al-Dahle

Wei Hsin Yao

Kingsuk Brahma

Christopher David Gadda

Gabriel M Hoffmann

Yafei Bi

Sang Young Youn

Yingxuan Li

Weijun Yao

Gregory Eric Rogers

Miroslav Baric

Timothee J Cazenave

Stefan Solyom

Carlos Alberto De Magalhaes Massera Filho

Nathaniel B Honka

Taif Ahmed Syed

Aspects of the present disclosure involve a method for determining a road vehicle velocity and slip angle. The current disclosure presents a technique for identifying a vehicle's velocity and slip angle, in the vehicle's coordinate frame. In one embodiment, two or more sensors are orthogonally located on the underside of the vehicle in order to obtain longitudinal and lateral velocity information for slip angle determination. In another embodiment, the two or more sensors can include an array of elements for beam steering and receiver beamforming. Spatial diversity is leveraged in identifying at least a slip angle and/or velocity of the vehicle. Doppler mapping is used as a means for slip angle determination and the clutter ridge of the Doppler map is embraced for identifying the slip angle.

Apparatus and method to measure slip and velocity

A control system for a vehicle includes a plurality of vehicle actuators that are operable to affect actual chassis-level accelerations, a vehicle intelligence unit that determines a motion plan, a vehicle motion control unit that determines a chassis-level motion request based on the motion plan, and a chassis control unit that determines actuator commands for the plurality of vehicle actuators based on the chassis-level motion request and actuator identity information that describes presently available actuators from the plurality of vehicle actuators.

Integrated chassis control

A control system for a vehicle includes a plurality of vehicle actuators that are operable to affect actual chassis-level accelerations, a vehicle intelligence unit that determines a motion plan, a vehicle motion control unit that determines a chassis-level motion request based on the motion plan, and a chassis control unit that determines actuator commands for the plurality of vehicle actuators based on the chassis-level motion request.

A charge pump that can be configured to operate in a first mode and a second mode is disclosed. The charge pump can comprise a charging capacitor coupled to a first node and configured to transfer a first DC voltage to the first node. The charge pump can also comprise a first output node and a second output node coupled to the first node. During the first mode, the first output node can be configured to output a second DC voltage based on the first DC voltage, and the second output node can be configured to output a third DC voltage based on the first DC voltage. During the second mode, the first output node can be configured to output the second DC voltage, and the second output node can be configured to output an AC voltage, the AC voltage being offset by the third DC voltage.

Charge pump having AC and DC outputs for touch panel bootstrapping and substrate biasing

A display may have a substrate layer to which a display driver integrated circuit and flexible printed circuit are bonded. The display driver integrated circuit may be provided with switches and control circuitry for controlling the operation of the switches during bond resistance measurements. Test equipment may apply currents to pads in the display driver integrated circuit through contacts in the flexible printed circuit while controlling the switching circuitry. Based on these measurements and the measurement of trace resistances in a dummy flexible printed circuit, the test equipment may determine bond resistances for bonds between the display driver integrated circuit and the display substrate and between the flexible printed circuit and the display substrate. Displays may have master and slave display driver integrated circuits that share coarse reference voltages produced by the master from raw power supply voltages.

Display driver integrated circuit architecture with shared reference voltages

Method for measuring display bond resistances

Devices and methods for reducing display-to-touch crosstalk are provided. In or more examples, an electronic display panel may include a pixel. The pixel may include a pixel electrode, a common electrode, and a first transistor having a first source coupled to a data line, a first gate coupled to a gate line, and a first drain coupled to the pixel electrode. The pixel may also include a second transistor having a second source coupled to the common electrode, a second gate coupled to the gate line, and a second drain coupled to a common voltage source. The second transistor may be configured to cause a parasitic capacitance between the gate line and the second drain of the second transistor and to reduce an effect of a parasitic capacitance between the gate line and the first drain of the first transistor.

Devices and methods for reduction of display to touch crosstalk

Systems and methods for calibrating an electronic display to reduce or eliminate artifacts are provided. One method for reducing or eliminating artifacts may involve baking the operational&#x2014;but not yet fully calibrated&#x2014;electronic display to reduce stray charge on the electronic display. After baking the display, the electronic display may be calibrated to reduce or eliminate flicker and/or mura artifacts

Systems and methods for mura calibration preparation

Systems and methods for efficiently generating display driver timing signals are provided. In one example, display driver circuitry of an electronic display may provide a negative voltage from a negative voltage supply to display control circuitry during a first period and may provide a positive voltage from a positive voltage supply to the display control circuitry during a second period. After providing the negative voltage during the first period but before providing the positive voltage during the second period, the display driver circuitry may precharge the capacitance of the display control circuitry to ground. In this way, the positive voltage supply substantially does not supply charge to raise the voltage on the capacitance of the display control circuitry from the negative voltage to ground.

Display driver precharge circuitry

The present disclosure relates to devices and methods for reducing power consumption of a display. One electronic display includes a first switch coupled between a first gate of a first transistor and a second gate of a second transistor to selectively connect the first gate to the second gate. The display includes a second switch coupled between the second gate of the second transistor and a third gate of a third transistor to selectively connect the second gate to the third gate. The display also includes driving circuitry that controls the first switch to connect the first gate to the second gate to share a first charge between the first and second gates. The driving circuitry also controls the second switch to connect the second gate to the third gate to share a second charge between the second and third gates. Accordingly, power consumption of the display may be reduced.

Devices and methods for reducing power consumption of a demultiplexer

Methods and devices employing mura prevention circuitry, are provided. In one example, a method may include supplying a first voltage pathway between a common electrode driver and a common electrode of an electronic display device and supplying a second voltage pathway between the common electrode driver and ground. Mura prevention circuitry may be supplied that activates the first voltage pathway when the electronic display device is turned on and an activation gate signal is provided from a gate corresponding to the common electrode driver. Further, the mura prevention circuitry may activate the second voltage pathway when the electronic display device is turned off or no activation gate signal is provided from the gate corresponding to the common electrode driver.

Devices and methods for common electrode mura prevention

Systems, methods, and devices are provided to calibrate an electronic display to reduce or eliminate mura artifacts. Such mura artifacts may be due to differential behavior of multiple common voltage layers (VCOMs) of the display. One method for reducing or eliminating such muras may involve setting pixels of an electronic display to a gray level and setting an operating parameter of the liquid crystal display to a starting value. An image of the pixels may be captured. Using the image, an average luminance of the pixels may be determined and the image may be amplified around the average luminance to enhance contrast of the image. When the amplified image substantially does not indicates the presence of a mura, the value of the operating parameter may be stored in the electronic display.

Systems and methods for reducing or eliminating mura artifact using contrast enhanced imagery

Systems, methods, and devices for calibrating an electronic display to reduce or eliminate a mura artifact are provided. The mura artifact may be due to differential behavior of common voltage layers (VCOMs) in the electronic display. One method for reducing or eliminating the mura artifact may involve setting pixels of the electronic display to a first gray level and measuring a luminance difference between light and dark areas of a mura artifact on the electronic display. A value of an operating parameter of the electronic display may be adjusted while monitoring the luminance difference measurement. A value of the operating parameter that causes the luminance difference measurement to be within a specified range of acceptable luminance difference measurement values may be stored in the electronic display.

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San Jose, CA, United States of America

David A Stronks