Intel Corporation

David A Stelliga

Simon S Chong

Anguo Tony Huang

Ryszard Bleszynski

Man Dieu Trinh

Systems and methods for assisting multiple protocol conversion in a network accelerator. A network device includes a transmit processing engine, a receive processing engine and one or more memories, each memory including one or more buffers for storing packets. When a packet is received, the receive engine adds a 4, 8, 12 or 16-byte tag to the front of the packet on a per-VC basis and stores the packet to a buffer. Additionally, the receive engine is able to add an offset to the starting address of the packet in the buffer relative to the beginning of the buffer. When a packet is to be transmitted, the transmit engine is able to transmit the packet from an address that is offset from the starting address of the buffer by one or more bytes. Additionally, the transmit engine is able to add one of several predefined packet headers on a per-packet basis.

Multi-protocol conversion assistance method and system for a network accelerator

A CBR/VBR traffic scheduler includes multiple CBR/VBR shapers to shape traffic over a wide range of peak cell rates for multiple CBR and VBR connection. Each shaper points to one or more VCs in a link list and includes a PCR counter initialized to a first value, an SCR counter initialized to a second and an arbitration counter. Each shaper is also connected to one of several clock sources, each having an associated clock cycle. A priority encoder, coupled to each arbitration counter, provides for determining priority between shapers having one or more associated VCs ready for transmission. Both the PCR counter and the SCR counter for each shaper is decremented during each associated clock cycle. For each shaper, when the PCR counter is decremented to a value of zero, the arbitration counter is initialized to a preset value and enabled for selection by the priority encoder. For each shaper, when the SCR counter is decremented to zero, a credit count parameter associated with each of the VCs in the associated link list is incremented by a predetermined value. The shaper having the lowest arbitration count value is selected by the priority encoder for cell transmission. When a shaper is selected for cell transmission, the associated link list of VCs is walked through in order. Only VCs that have a credit count parameter above a threshold value are transmitted.

CBR/VBR traffic scheduler

Systems and methods for storing, or caching, VC descriptors on a single-chip network processor to enhance system performance. The single-chip network processor includes an on-chip cache memory that stores VC descriptors for fast retrieval. When a VC descriptor is to be retrieved, a processing engine sends a VC descriptor identifier to a content-addressable memory (CAM), which stores VC descriptor identifiers in association with addresses in the cache where associated VC descriptors are stored. If the desired VC descriptor is stored in the cache, the CAM returns the associated address to the processing engine and the processing engine retrieves the VC descriptor from the cache memory. If the VC descriptor is not stored in the cache, the CAM returns a miss signal to the processing engine, and the processing engine retrieves the VC descriptor from an off-chip memory. In this manner, VC descriptors associated with high bandwidth VCs are stored to the cache and retrieved much quicker from the cache than from the off-chip memory.

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Pleasanton, CA, United States of America

David A Stelliga