Advanced Micro Devices Corporation

David A Spilo

Melanie D Typaldos

Bruce A Loyer

Robert Paul Gittinger

Thai H Pham

Chongjun (June) Jiang

Robert D Bryfogle

Timothy J Baldwin

Robert I Pinkerton, Jr

Martin Schuessler

Bobby I Pinkerton, Jr

A microcontroller includes a direct memory access unit that compresses and decompresses data and transfers from one block of memory to another. Specifically, word size data can be read, one byte discarded, and stored as consecutive, byte size data. This can be used in conjunction with an extended read and extended write asynchronous serial port that stores status information along with data. Once the status information is processed, the status is stripped by performing the &ldquo;compressive&rdquo; DMA.

Data compression or decompressions during DMA transfer between a source and a destination by independently controlling the incrementing of a source and a destination address registers

In a microcontroller employing a buffer descriptor ring direct memory access (DMA) unit, transmission of a packet can be split between multiple buffers. If an error occurs during the transmission of one of the buffers, the buffer descriptor ring DMA unit includes a provision that allows the software to reset the DMA channel to the first buffer containing the failed packet and to restart the transmission of the failed packet, rather than proceeding to the next packet.

System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again

A microcontroller architecture and an associated method are presented which provide for testing of an &ldquo;on-chip&rdquo; memory unit. The microcontroller includes a microcontroller core, the memory unit, a set of input/output (I/O) pads, and an input/output (I/O) pad interface unit, all formed upon a single monolithic semiconductor substrate. The microcontroller core executes instructions and generates data. The memory unit is coupled to the microcontroller core and stores data. The memory unit may include a common static random access memory (SRAM) device having multiple memory cells with load devices permitting static operation. A data latch within the memory unit samples retrieved data and provides the retrieved data to the microcontroller core. The data latch is responsive to a data latch control (DLC) signal produced by the I/O pad interface unit. The I/O pad interface unit receives a signal from one or more members of the set of I/O pads and generates the DLC signal in response to the signal. In a testing mode of the microcontroller, the DLC signal is asserted, and latching of retrieved data occurs on the next transition of a system clock cycle following assertion of the row select signal. Thus in the testing mode, the length of a time period between assertion of the row select signal and the latching of the retrieved data by the data latch is variable and dependent upon the duty cycle of the system clock signal.

Microcontroller architecture and associated method providing for testing of an on-chip memory device

A processor-oriented device provides a watchdog timer having a test mode programmable reset. When the device is placed in a test mode by pulling a test mode hardware pin during a reset of the timer and then an appropriate write key is provided to the timer, a watchdog timer reset count is writeable, allowing for a programmable duration for a watchdog timer reset. The watchdog timer reset count may be a reset duration value maintained by a watchdog timer reset counter. Based on both a test mode signal from watchdog timer test mode enable logic and a write key, watchdog timer reset write enable logic enables writes to the watchdog timer reset count.

Test mode programmable reset for a watchdog timer

A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that polls buffer descriptors when in idle mode. This polling is to determine whether the software has set up a buffer or group of buffers transmission and transfer ownership of those buffers to the DMA unit. To reduce interrupt latency and bandwidth occupation, the polling of these buffer descriptor ownership flags is staggered for the DMA channels. For example, if eight DMA channels are implemented, the polling of their buffer descriptors can be distributed throughout a 1.28 millisecond polling interval.

Staggered polling of buffer descriptors in a buffer descriptor ring direct memory access system

A processing unit having a CPU core, an integrated RAM and a test unit, which may be implemented in either a test unit, which may be implemented in either hardware or software. A built-in self-test of the RAM is designed to run concurrently with the functional vectors used to test the CPU core. Once the core tests have been activated, a control register may be written to by which will activate the built-in self-test. Thus, the BIST and core testing may overlap to minimize test time.

Technique for incorporating a built-in self-test (BIST) of a DRAM block

A microcontroller includes an integrated memory and an integrated DMA controller. During testing, the DMA controller is used to perform read/write tests of background patterns and complements thereof to the integrated memory. The integrated memory need not contain the BIST logic typically required of integrated memories. By using the DMA controller to perform BIST-type testing, the tests are not hardware-bound. Typically, the BIST logic included in integrated memories is designed and tested during the design of the microcontroller. This design and test time is replaced by a (possibly shorter) task of generating test vectors for the requisite DMA transfers. The risk of having an error in the BIST test is reduced using the present testing method. Formerly, if BIST logic was found to be in error, new manufacturing masks for the microcontroller were required to repair the problem. A large time and monetary investment was required. The present method allows for correction and variation in the testing by resimulating the tests and creating new test vectors. The new test vectors may then be applied to previously manufactured microcontrollers.

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Austin, TX, United States of America

David A Spilo