Ag Communication Systems Corporation

David A Smiley

Edward M Horiuchi

Daryl P Slaviero

A system for programming field programmable devices (FPDs) of different types across different boards. An in-system programmable master (ISPM) communicates over a bus to in-system programmable slaves (ISPSs) on one or more boards. FPDs on each board are connected into chains of the same type, and each chain is connected to an ISPS located on the board. The ISPM uses a packet protocol to communicate with all ISPSs in a system. Each packet comprises an ISPS address field, a chain select field, and a command field. Each ISPS reads packets addressed to it, and decodes and transmits the commands to the selected FPD chain in a protocol appropriate to the chain.

System for programming field programmable devices

A multipoint video conferencing system in which the video conferencing terminals are in a daisy-chain arrangement with the head-of-chain terminal connected to the ATM network. ATM cells are relayed from the ATM network downstream to the last terminal, and from each terminal upstream to the network. Each video conference terminal has a video program input port provisioned with a unique ATM address, and a plurality of video program out ports, each provisioned with one of the video program input port addresses. ATM cells generated from each video program input port are transmitted upstream to the ATM network where they are relayed back to the head-of-chain terminal and then downstream to the last terminal. Each video conferencing terminal may also receive ATM cells having addresses that match the addresses provisioned for its video program output ports. These cells are converted to analog video programs and transmitted out the associated video output ports. In this manner, an ATM cell may be used on several video conferencing terminals.

Video conference system with ATM cell reuse

A clock enabling circuit that generates an output clock signal such that when the enable output signal changes to a logical false, the output clock signal returns to its steady-state value in a manner that does not produce any glitches, and preserves the duty cycle of the input clock. The circuit comprises a first D flip-flop that is positive-edge triggered, a second D flip-flop that is negative-edge triggered, and a two-input AND gate. The first flip-flop has the D input connected to a constant positive voltage, the positive-edge triggered clock input connected to the input clock signal, the Q output connected to the AND gate, and the Q-complement output connected to the asynchronous reset of the second flip-flop. The second flip-flop has the D input connected to the enable output signal, the negative-edge triggered clock input connected to the input clock signal, the Q output connected to the asynchronous reset of the first flip-flop, and the Q-complement output connected to the AND gate. The output of the AND gate is the output clock signal.

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Peoria, AZ, United States of America

David A Smiley