Rambus Inc.

Apple Inc.

David A Secker

Ravindranath T Kollipara

Ian P Shaeffer

Suresh Rajan

Kyung Suk Oh

Brian S Leibowitz

Wayne S Richardson

Lawrence Lai

Fan Ho

Akash Bansal

Amir Amirkhany

Steven Cameron Woo

Sanjay Dabral

Abhijit Mukun Abhyankar

Jun Zhai

Vidhya Ramachandran

Chanh Vi Tran

Chi-Ming Yeung

Ralf M Schmitt

Wenjie Mao

Ling Yang

Ying Ji

Donald R Mullen

Huabo Chen

Zhenggang Cheng

Ely K Tsern

Ming Chu Li

Thomas J Giovannini

John M Wilson

Mahesh S Hardikar

Wendemagegnehu Beyene

Arun Vaidyanath

Yoshie Nakabayashi

Nitin Juneja

Robert R Atkinson

Shajith Musaliar Sirajudeen

Rajasekaran Swaminathan

Joong-Ho Kim

Nirmal Jain

Adrian F Torres

A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Folded memory modules

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Memory device comprising programmable command-and-address and/or data interfaces

Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

High performance, high capacity memory modules and systems

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Power management system switched capacitor voltage regulator with integrated passive device

The connector portion of a flex connector may be integrated into a socket, by forming a complete cutout in the socket in which the connector is located, or by forming the socket with a portion having a reduced thickness relative to the rest of the socket, with the connector being positioned in this portion of reduced thickness between the socket and an MLB. Another flex connector may be formed vertically above the first flex connector, mounted to the top surface of the package and clamped in place by a heat sink on top of the stack. Providing both top and bottom flex connectors may multiply the number of available connections for a given footprint. A heatsink positioned on top of the stack may include a spring assembly on a bottom portion to engage specified portions of the stack with a predefined force to ensure correct loading.

Socket with integrated flex connector

Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

Memory mirroring

Growing community of inventors

San Jose, CA, United States of America

David A Secker