Lattice Semiconductor Corporation

David A Rhein

John Schadt

Warren L Ziegenfus

William B Andrews

Fulong Zhang

Zheng Chen

Larry Fenstermaker

Ming Hui Ding

Anthony K Myers

Brian W Yeager

Stephen R Cebenko

A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

Programmable logic devices with integrated standard-cell logic blocks

A base transistor structure and associated programmable cell library compatible with standard cell computer-aided design (CAD) tools are disclosed. In an illustrative embodiment of the invention, the base transistor structure is symmetric about one or more axes, and extends only a single grid of a standard cell CAD tool in width. The base transistor structure is advantageously configured in a manner that permits the utilization of gate isolation to separate active transistors in adjacent base transistor structures. The base transistor structure can be used to implement a programmable cell technology that is fully compatible with standard cell CAD tools.

Integrated circuit base transistor structure and associated programmable cell library

Growing community of inventors

Reading, PA, United States of America

David A Rhein