Digital Equipment Corporation

Microsoft Technology Licensing, LLC

Digital Equipment Company

David A Orbits

David N Cutler

Richard T Witek

Wayne M Cardoza

Dileep P Bhandarkar

H Bruce Butts, Jr

Kenneth D Abramson

Balan Sethu Raman

Sudarshan Anand Chitre

Praerit Garg

Chris J Guzak

Jason Fergus Moore

John M Parchem

Darrel D Donaldson

Douglas D Williams

Eric R Flo

Shaun A Kaasten

Jeffrey M Saathoff

David M Robinson

Mark N Howard

Disclosed is a data synchronization service for use in a peer-to-peer computing environment. Selected data objects are copied onto selected computing devices. A service running on each device monitors data objects for changes. When a change is detected, the service sends a change notification to the other devices so that they can update their copies of the data object. A user can access a data object from any device, knowing that he will retrieve the latest version of the data object. Instead of incurring the costs of storing a large file on every device, a user 'ghosts' the file on some devices. A ghosting device stores only metadata about the file rather than the entire file. The user accesses the file through the ghost: access requests are sent to a device that holds the actual contents, and those contents are presented to the user as if they were stored locally.

Method and system for synchronizing data shared among peer computing devices

Described is a system and method for replicating each of a set of resources to a subject computer in a replica set prior to making use of a resource in the set of resources. The set of resources includes resources that are dependent upon each other for a proper functioning of the group. A manifest file that identifies each resource in a group of interrelated resources is used. The manifest file is generated at one computer in the replica set (typically the computer at which a modification to one of the interrelated resources occurred). When the modification occurs to one of the set of resources, the manifest file is transmitted (e.g., itself replicated) to each computer in the replica set. The manifest file includes an indicator that identifies the manifest file as a special file. When received at another computer in the replica set, a service evaluates the manifest file to identify whether the appropriate versions of the identified resources exist at the receiving computer. If not, the service at that computer awaits the receipt of each resource. The wait period may include delaying the execution of an application associated with (or even included within) the manifest file from launching. Alternatively, the FRS could simply disallow access to one or more resources identified in the manifest file until all have arrived. When all have arrived, the FRS releases control of the identified resources, which may then operate or be accessed in the ordinary manner.

System and method for reliably replicating data

System and method for replicating data in resource sets

A computer system executing virtual memory management and having a cache is operated in a manner to reduce cache misses by remapping pages of physical memory from which cache misses are detected. The method includes detecting cache misses, as by observing cache fill operations on the system bus, and then remapping the pages in the main memory which contain the addresses of the most frequent cache misses, so that memory references causing thrashing can then coexist in different pages of the cache. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain at the same virtual address, by simply updating the page-mapping tables to reflect the new physical location of the page, and copying the data from the old page frame to the new one. The primary feature of the invention is to add bus activity sampling logic to the CPU and enhance the operating system to allow the operating system to detect when cache thrashing is occurring and remap data pages to new physical memory locations to eliminate the cache thrashing situation.

Enhanced cache operation with remapping of pages for optimizing data

A method of scheduling processes on a symmetric multiprocessing system that maintains process-to-CPU affinity without introducing excessive idle time is disclosed. When a new process is assigned, the process is identified as young and small, given a migtick value and assigned to a specific CPU. If the priority of a process placed on a run queue is above a threshold, the high priority count of the assigned CPU is incremented. At predetermined clock intervals, an interrupt occurs that causes the migtick value of running processes to be decremented. Then each CPU is tested to determine if its high priority count is greater than zero. CPUs having high priority counts greater than zero are tested to determine if any processes having a priority greater than the priority of the running process are assigned. If higher priority processes are assigned to a CPU having assigned processes lying above the threshold, a context switch takes place that results in the higher priority process being run. At regular intervals, a migration deamon is run to load balance the multiprocessor system. First, a large/small process threshold is determined. Then processes whose migtick values are below a migtick threshold (e.g., 0) are identified as old. Old processes then are identified as large or small processes based on their memory usage. Next, a determination is made of whether the small and large process load balances of the system can be improved. If either or both can be improved, the smallest small and/or the smallest large processes are migrated from their assigned CPU to the CPU with, as the case may be, the least large or the least small processes.

Affinity scheduling of processes on symmetric multiprocessing systems

An instruction eases exception handling in a data processing system having one or more parallel pipelined execution units by permitting the central processing unit to complete instructions currently being processed by the execution units, but preventing further instructions from being initiated until all currently executing instructions have been completed and all outstanding exception conditions have been resolved. After all the instructions preceding the DRAIN instruction of the present invention in the program instruction sequence have been executed, the central processing unit can continue to execute the sequential program instructions when no arithmetic exception has been identified, or can invoke an exception handling procedure when an arithmetic exception has been identified. The instruction is typically positioned in an instruction sequence after an instruction that has high degree of probability of resulting in the identification of an arithmetic exception condition. The DRAIN instruction permits the source of the exception to be localized and permits the response to all arithmetic exceptions associated with instructions initiated before the DRAIN instruction, but identified after the execution of the DRAIN instruction, to be handled in the same context environment in which the instruction was initiated.

Method for synchronization of arithmetic exceptions in central

In a data processing system, apparatus and method for controlling the type of processing to which data signal groups can be subjected includes a page table entry format having a multiplicity of field positions for storing signals defining page access rights. In addition to the read/write access control, the signal group access rights can be determined by the current mode of operation of the data processing unit and the intended activity of the addressed instruction or data element (i.e., read, write or execute).

Apparatus and method for main memory unit protection using access and

A coherent coupled memory multiprocessor computer system that includes a plurality of processor modules (11a, 11b . . . ), a global interconnect (13), an optional global memory (15) and an input/output subsystem (17,19) is disclosed. Each processor module (11a, 11b . . . ) includes: a processor (21); cache memory (23); cache memory controller logic (22); coupled memory (25); coupled memory control logic (24); and a global interconnect interface (27). Coupled memory (25) associated with a specific processor (21), like global memory (15), is available to other processors (21). Coherency between data stored in coupled (or global) memory and similar data replicated in cache memory is maintained by either a write-through or a write-back cache coherency management protocol. The selected protocol is implemented in hardware, i.e., logic, form, preferably incorporated in the coupled memory control logic (24) and in the cache memory controller logic (22). In the write-through protocol, processor writes are propagated directly to coupled memory while invalidating corresponding data in cache memory. In contrast, the write-back protocol allows data owned by a cache to be continuously updated until requested by another processor, at which time the coupled memory is updated and other cache blocks containing the same data are invalidated.

Coupled memory multiprocessor computer system including cache coherency

A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block in another processor's cache and the request is pending completion. All subsequent read requests for the data block during the pendency of the first request are inhibited until completion of the first request. Also provided in the memory directory for each data block is a field for identifying the processor which owns the data block in question. Data block ownership information is used to determine where requested owned data is located.

Cache coherency protocol for multi processor computer system

In a multiprocessor data processing unit, a data element in the main memory unit, that has system wide significance, can have a requirement that this data element be altered in a controlled manner. Because other data processing units can have access to this data element, the alteration of the data element must be synchronized so the other data processing units are not in the process of altering the same data element simultaneously. The present invention includes an instruction that acquires access to an interlock signal in the main memory unit and initiates an interlock in the main memory unit, thereby excluding other data processing units from gaining access to the interlock signal simultaneously. The instruction causes the data element related to the interlock signal to be transferred to the data processing unit where the data element is saved, can be entered in mask apparatus and then have a quantity added thereto. The altered data element is returned to the main memory unit location and the main memory interlock signal is released, thereby completing the instruction.

Apparatus and method for synchronization of access to main memory signal

In a data processing system, an instruction is disclosed that generates a fault when a predetermined register position (e.g., the low or least significant bit position) has a predetermined logic signal (e.g., a logic `0` signal). This instruction provides a mechanism to determine when a Boolean value indicates a presence of a fault condition and provides a mechanism to generate the fault when present. For example, in arrays of memory locations that can be addressed by a program, this instruction can respond to the presence of an array address (or reference) that is outside the prescribed bounds of the array. When an invalid address is identified, a signal is entered in the low (i.e., least significant) bit position of a processor scalar register. The instruction repertoire includes a Fault on Low Bit Clear instruction that tests the contents of the scalar register low bit position, and when a logic `0` signal is found therein, an exception signal is generated and applied to the control program of the data processing system.

Apparatus and method for data induced condition signalling

An adaptive memory management method for coupled memory multiprocessor computer systems is disclosed. In a coupled memory multiprocessor system all the data and stack pages of processes assigned to individual multiprocessors are, preferably, located in a memory region coupled to the assigned processor. When this becomes impossible, some data and stack pages are assigned to global memory or memory regions coupled to other processors. The present invention is a method of making certain that the most referenced data and stack pages are located in the coupled memory of the processor to which a specific process is assigned and lesser referenced pages are located in global memory or the coupled memory region of other processors. This result is accomplished by sampling the memory references made by the processors of the computer system and causing the most recently referenced pages in each coupled memory region to be maintained at the head of an active page list. References to remote data and stack pages are stored in a remote page hash table. Remote pages are pages stored in global memory or in coupled memory other than the coupled memory of the processor to which the process owning the pages is assigned. Any remote data and stack pages referenced more frequently than pages stored in a processor's coupled memory region are transferred to the processor's coupled memory region. If a processor's coupled memory region is tight, pages are transferred from the processor's coupled memory region to global memory or to the coupled memory region of another processor.

Adaptive memory management method for coupled memory multiprocessor

A method of managing the memory of a CM multiprocessor computer system is disclosed. A CM multiprocessor computer system includes: a plurality of CPU modules 11a . . . 11n to which processes are assigned; one or more optional global memories 13a . . . 13n; a storage medium 15a, 15b . . . 15n; and a global interconnect 12. Each of the CPU modules 11a . . . 11n includes a processor 21 and a coupled memory 23 accessible by the local processor without using the global interconnect 12. Processors have access to remote coupled memory regions via the global interconnect 12. Memory is managed by transferring, from said storage medium, the data and stack pages of a process to be run to the coupled memory region of the CPU module to which the process is assigned, when the pages are called for by the process. Other pages are transferred to global memory, if available. At prescribed intervals, the free memory of each coupled memory region and global memory is evaluated to determine if it is below a threshold. If below the threshold, a predetermined number of pages of the memory region are scanned. Infrequently used pages are placed on the end of a list of pages that can be replaced with pages stored in the storage medium. Pages associated with processes that are terminating are placed at the head of the list of replacement pages.

Memory management method for coupled memory multiprocessor systems

In a data processing system employing microcode techniques, complex sequences of microinstructions can be initiated by application of a single macroinstruction. These complex sequences of microinstructions are typically noninterruptible and therefore the execution of a macroinstruction is atomic (i.e., executed as a single entity). Data processing systems that do not employ microcode typically have simpler macroinstruction sets that do not provide for a similar atomicity for complex instruction sequences. In order to obtain the same atomicity of instruction execution and to provide a nonmicrocoded data processing system with the capability to execute complex instruction sequences as an atomic operation, the nonmicrocoded data processing system is provided with a third mode, in addition to the (nonprivileged) user mode and the (privileged) kernel mode, of operation that permits the execution of instruction sequences with interrupting events disabled and certain functions and apparatus enabled to facilitate instruction sequence execution.

Providing a data processor with a user-mode accessible mode of

In a data procesing system having a kernel mode (i.e., for executing privileged instructions) and a user mode of operation, apparatus for responding to interrupt conditions includes a first register, subject to the control of the currently executing program for enabling the generation of a mode-related interrupt signal and includes a second register for indicating the presence of a pending mode-related interrupt condition and a third register for requesting a mode-related interrupt be entered in the second register. The mode of operation and the enable and pending interrupt condition registers are monitored and when the signals in the two registers have the appropriate relationship, an interrupt signal is generated to which a control program will respond. The contents of the first register can be controlled by the currently executing program which can control the enabling signal for the currently executing mode. The pending interrupt condition and the request registers may be accessed only from the privileged mode of operation.

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Redmond, WA, United States of America

David A Orbits