Lsi Logic Corporation

David A Morgan

Viswanathan Lakshmanan

Richard D Blinne

James Arnold Jensen

Michael Josephides

Christopher J Tremel

Tom R O'Brien

A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.

Chip design method for designing integrated circuit chips with embedded memories

A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an area cut out of the child macro corresponding to the location of the cell.

Method of repeater insertion for hierarchical integrated circuit design

A Register Transfer Language (RTL) annotation software tool that: (1) automatically calculates new RTL of a circuit to facilitate subsequent RTL level Engineering Change Orders (ECOs) on a circuit where gate level changes have occurred during layout; and (2) automatically calculates a gate level netlist that corresponds to the RTL ECO which can be fed to modern layout tools with minimal disruption to the existing layout. In a preferred embodiment, the tool is software driven, iterative, and tracks any changes that need to be made for any given circuit described by a hardware description language (HDL) though a series of intermediate and preliminary data files. The software receives input in the way of user input, constraints, and an RTL description for a pre-ECO circuit, and outputs the post-layout annotated RTL description. Subsequent ECOs are taken as input from the user in the form of a modified annotated RTL description and the software produces a corresponding gate level netlist for the ECO circuit, all the while preserving as much of the data generated during this process to avoid wasteful duplication of effort.

RTL annotation tool for layout induced netlist changes

In this method for hierarchical extraction of interconnect parasitic data for integrated circuits, a representation of coupled interconnects and polygon data copied from an upper level to a lower level is simplified so that the coupled interconnects and the polygon data are considered to be ground wires. This method also features instance-specific management of hardmac data from copied hardmac views to create SPEF files using both chip level and macro level back-annotation in a hierarchical representation.

Full-chip extraction of interconnect parasitic data

Methods and apparatus for use with electronic circuit design tools to define and test multiple power and ground domains within an electronic circuit design. The present invention defines a power and ground specification associated with a CAD/CAE tools design database. To build the power and ground specification, first, power and ground domains are defined and the circuit design is partitioned into one or more groups of devices which correspond to the power and ground domains. Second, power and ground signals are associated with these defined groups of devices. Lastly, this information is stored within a power and ground specification integrated with the information within the design database to allow the CAD/CAE tools to test the multiple power and ground domains within the IC or circuit board design.

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Fort Collins, CO, United States of America

David A Morgan