Compaq Computer Corporation, Inc.

David A Miller

Kenneth A Jansen

Paul R Culley

Montgomery C McGraw

Darren John Cepulis

Mark E Taylor

Javier F Izquierdo

A processor-based system includes a processing unit. The processing unit includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. The processing unit is reset in response to a system reset signal being asserted at a reset input node and only selected portions of the processing unit are reset in response to a partial-reset signal being asserted at a partial-reset input node. The system can also include a number of other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.

Processor based system with system wide reset and partial system reset capabilities

Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.

Resetting multiple processors in a computer system

A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. Each processing unit is reset in response to a system reset signal but only selected portions of the processing units are reset in response to a partial-reset signal. The system can also include a number other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.

Multi-processor system with system wide reset and partial system reset

Common reset ROM

A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.

Method and apparatus for independently resetting processors and cache

Apparatus for initializing a multiple processor computer system using a

Method for initializing a multiple processor computer system using a

Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.

Method and apparatus for resetting multiple processors using a common ROM

A method and apparatus for arbitrating between multiple processors that can be incorporated into an arbitration scheme that is designed to include only a single processor. The method includes consolidating the individual bus requests of each processor into a single bus request supplied to the single processor arbitration scheme. When control of the bus is allocated to the single processor, the multiprocessor arbitration arbitrates among the processors who requested the bus. The bus protocol used includes a least recently used method for granting bus access to the multiple processors coupled with a means for giving one processor priority over the others for access to the bus. The protocol also includes protection from interruption for the respective processor in control of the bus for a preset period of time.

Two level system bus arbitration having lower priority multiprocessor

Method and apparatus for interfacing audio equipment and a computer system. Compressed parallel digital audio data originating on a system bus associated with the computer system is transmitted to a first data interface where the compressed parallel digital audio data is converted into compressed serial digital audio data. The compressed serial digital audio data is then transmitted to a second data interface associated with a digital signal processor. The second data interface routes the compressed serial digital audio data from the first data interface to the digital signal processor where the data is expanded and then returned to the second data interface. The second data interface then routes the processed serial digital audio data to a digital-to-analog converter where the processed serial digital audio data is converted to analog audio data and transmitted to the audio equipment for output. Analog audio data produced by the audio equipment is transmitted to a analog-to-digital converter for conversion into serial digital data. The analog-to-digital converter then transmits the serial digital audio data to the second data interface which routes the data to the digital signal processor. The digital signal processor compresses the serial digital audio data and returns the data to the second data interface. The second data interface then routes the compressed serial digital audio data to the first data interface where the data is converted into compressed parallel digital audio data and transmitted to the computer system bus.

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Houston, TX, United States of America

David A Miller