Rockwell Collins, Inc.

David A Miller

Daniel E Mazuk

Brent James Nelson

Mark A Kovalan

James Matthew Zaehring

David C Matthews

Nicholas H Bloom

Clifford R Klein

Eric N Anderson

Peter J Morgan

Carl J Henning

J Perry Smith

Neal J Bohnenkamp

Savio N Chau

Richard M Bradford

Charles F Steffen

Daniel J Goiffon

Robert H Pulju

A system includes a first and at least one second processing circuit, a configuration engine, and a switch. The configuration engine stores a virtual link configuration for a plurality of virtual links, which indicates a priority and a predetermined network pathway for communicating data packets from the first processing circuit to the at least one second processing circuit. The configuration engine automatically assigns priority to a first virtual link of the plurality of virtual links based on at least one of latency or jitter. The switch receives a first data packet from the first processing circuit. A first virtual link identifier is extracted from the first data packet. A first priority and a first predetermined network pathway corresponding to the first virtual link identifier from the virtual link configuration are retrieved. The first data packet is transmitted along the first predetermined network pathway based on the first priority.

Systems and methods for automatic priority assignment for virtual links

A device for avionics full-duplex switched Ethernet (AFDX) communication can include a transmit port for transmitting AFDX data and a processor. The processor can be configured to obtain AFDX data frames for transmission over a plurality of sub-virtual links (subVLs) of a virtual link (VL), and maintain, for each of the plurality of subVLs, a corresponding data queue by storing AFDX data frames associated with that subVL in the corresponding data queue. The processor can transmit the AFDX data frames from the plurality of data queues on the plurality subVLs via the transmit port according to a scheduling policy that is based on subVL prioritization. The scheduling policy that is based on subVL prioritization can include static priority (SPn) scheduling, earliest deadline first (EDF) scheduling, or least laxity first (LLF) scheduling.

Scheduling mechanisms for end system SUBVLs

A method for optimizing the design of backplane and field bus routing for avionics network architectures determines a solution space of valid configurations defined by the intersection of universes corresponding to potential aircraft sensor locations, the data content relationships for each hosted application executing on the aircraft computing center, potential remote data concentrator (RDC) configurations, and potential backplane/field bus configurations for the avionics network architecture. The method includes identifying within the solution space, via an optimization engine, optimal configuration solutions of a desired optimality level based on connectivity constraints, system survivability constraints providing spatial separation of primary and redundant sensor and data collection systems, system robustness constraints associated with minimum functional capabilities for continued safe flight and landing capability, and an objective function characterizing overall desirability.

System and method for optimizing design of aircraft backplane spatial separation

A homomorphic encryption based high integrity computing system including a processing system including a single-string computation channel configured to receive encrypted input data from at least one data source. The processing system includes at least one processor hosting at least one hosted function. The processor is configured to provide high integrity homomorphic encryption-based computations thereon. This enables isolated channel computations within a single physical computation channel. The at least one processor provides encrypted output data, wherein the encrypted output data is configured to enable computational integrity validation by a receiver.

Homomorphic encryption based high integrity computing system

Systems and methods for predicting and managing computation derations that may occur in multi-core processors are disclosed. The method may include: determining effects of multi-core contentions on a particular core of a multi-core processor; determining effects of single-core contentions on a particular hosted function hosted on the multi-core processor; determining an adjustment time to a baseline activation time for the particular hosted function, wherein the adjustment time plus the baseline activation time overcome the effects of multi-core contentions and single-core contentions at a predetermined probability goal; and adjusting a computation time requirement of the particular hosted function to include the adjustment time and the baseline activation time.

Prediction and management of multi-core computation deration

A system and method for ensuring a minimum required availability of a Hosted Function (HF) may retain an entirety of a cache content between separate instances of one or more HF which may share a cache resource. Based on controlling a relationship between an unavailability of cache memory desired by the HF to a probability of the available cache being unusable by the HF, each activation period may be variable within a tolerance to achieve a certification strategy. The approach may statistically characterize a best case, expected case, and worst case of cache availability. The system and method may determine a quality of the cache state at the activation of a particular HF and, based on the statistical analysis of that quality over time, determine a desired derated activation period for each HF to achieve a minimum level of computational availability for successful activation of the HF.

Cache retention analysis system and method

The node communication controller (NCC) suitable for use in a line-replaceable unit (LRU) of a modular avionics system may include one or more embedded processors configured to host one or more functions associated with at least one avionics module of an avionics system, an input/output (I/O) controller, and one or more I/O ports, wherein the I/O controller is configured to route data between the one or more embedded processors and the at least one avionics module via the one or more I/O ports and a network communication bus, wherein the I/O controller is further configured to route data between a host processor of the LRU and an additional avionics module via the one or more I/O ports and the network communication bus.

Integrated modular avionics system with distributed processing

A data network includes a plurality of end systems; a plurality of line data buses connected to the end systems; and a plurality of switches connected to the line data buses and to other switches via trunk data buses to define a star topology. The switches and end systems are configured to operate asynchronously. Each switch includes a number of packet schedulers for managing the transmission of received data flow. A number of effective line rate utilization mechanisms are each associated with a respective packet scheduler for providing the service rate of that packet scheduler. Switch egress ports transmit the received data flow. Each switch egress port has a defined configured effective transmission rate. Each effective line rate utilization mechanism reduces the utilization rate to the defined configured effective transmission rate.

Data network with constrained switch transmission rates

A 'per flow' flow monitor is operatively associated with each ingress port of the switch of the data network, for monitoring the arrival data flow on each flow in defined traffic constraint envelopes containing frames. An eligibility time computation mechanism computes an eligibility time at which arriving frames on each flow will be conformant to the defined traffic envelope to the ingress port given past frame arrivals on that same flow. A holding mechanism holds the arriving frames on each flow until the eligibility time is reached. A release mechanism releases the arriving frames on a flow at the eligibility time. The flow monitor, computation mechanism, holding mechanism, and release mechanism cooperate to provide an 'per flow' traffic shaping function in conformance with delay and delay-jitter bound, frame loss probability, and bandwidth provisioning requirements, thus allowing the switch to enforce the traffic constraint envelope for each flow.

Data network with 'per flow' flow monitoring

A multi-core processor system includes a number of cores, a memory system, and a common access bus. Each core includes a core processor; a dedicated core cache operatively connected to the core processor; and, a core processor rate limiter operatively connected to the dedicated core cache. The memory system includes physical memory; a memory controller connected to the physical memory; and, a dedicated memory cache connected to the memory controller. The common access bus interconnects the cores and the memory system. The core processor rate limiters are configured to constrain the rate at which data is accessed by each respective core processor from the memory system so that each core processor memory access is capable of being limited to an expected value.

Multi-core processor system configured to constrain access rate from memory

Each switch of the data network includes a number of switch ingress ports for receiving arrival data flow. An aggregate flow monitor is operatively associated with each ingress port for monitoring the aggregate arrival data flow in defined traffic constraint envelopes containing frames. An eligibility time computation mechanism computes an eligibility time at which arriving frames to an ingress port will be conformant to the defined traffic envelope to the ingress port given past frame arrivals. A holding mechanism holds the arriving frames to the ingress port until the eligibility time is reached. A release mechanism releases the arriving frames for forwarding at the eligibility time. The aggregate flow monitor, the eligibility time computation mechanism, the holding mechanism, and the release mechanism cooperate to provide an aggregate traffic shaping function, thus allowing the switch to enforce the traffic constraint envelope for each ingress port.

Data network with aggregate flow monitoring

The present disclosure is directed to a passive optical avionics network system and method. A avionics network system may comprise: (a) a passive optical network, the passive optical network comprising an optical repeater; and (b) an avionics module operably coupled to the passive optical network. An integrated modular avionics (IMA) system may comprise: (a) a line-replaceable unit (LRU), the LRU comprising: (i) a processing unit; and (ii) an optical line terminal (OLT); (b) an optical repeater; (c) at least one optical network unit (ONU); and an avionics module operably coupled to the at least one ONU. A method for avionics network communication may comprise: (a) receiving optical avionics data signals; (b) monitoring the optical avionics data signals for compliance with a communications protocol; and (c) regulating transmission of the optical avionics data signals according to compliance with the communications protocol.

Passive optical avionics network including optical repeater

A multi-core processor system including a main processor, an internal EPON bus, and a plurality of secondary core processors. The main processor includes a processing unit; an offload engine operatively connected to the processing unit for routing data to and from the processing unit; a plurality of main processor optical network units (ONU's) operatively connected to the offload engine; and, a dual optical line terminal (OLT) operatively connected to the offload engine. The internal EPON bus is operatively connected to the OLT. The plurality of secondary core processors are located physically separate from the main processor, each secondary core processor having a respective secondary core processor ONU being operatively connected to the main processor via the internal EPON bus. A number of the multi-core processor systems can be used to form an integrated modular avionics (IMA) system when operatively connected to remote data concentration components via an external EPON bus connected to the dual OLTs of the multi-core processor systems.

Secondary core ONU to OLT via internal EPON bus coupled multi-core processor for integrated modular avionic system

The present disclosure is directed to a passive optical avionics network system and method. A passive avionics network may comprise: (a) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the OLT and the ONU; and (d) an avionics module operably coupled to the ONU. An integrated modular avionics (IMA) system may comprise: (a) a line-replaceable unit (LRU), the LRU comprising: (i) a processing unit; and (ii) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the LRU and the ONU; and (d) an avionics module operably coupled to the ONU. A method for avionics network communication may comprise: (a) providing avionics data; (b) transmitting the avionics data via a fiber optic network; (c) receiving the avionics data; and (d) controlling functionality of an avionics module according to the avionics data.

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Swisher, IA, United States of America

David A Miller