Intel Corporation

David A Leak

Rodney R Rozman

Joseph H Salmon

Robert E Larsen

Peter K Hazen

Jerry A Kreifels

Charles W Brown

Christopher John Haid

Vishram P Dalvi

Alan E Baker

Thomas C Price

Fasil G Bekele

Kerry Dean Tedrow

Kurt B Robinson

Sachidanandan Sambandan

Dhiraj Parmar

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Nonvolatile writeable memory with program suspend command

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register, and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Method and apparatus for suspending the writing of a nonvolatile

A method and apparatus for using address transition detection in a device to reduce power consumption. An address transition detection and power reduction circuit for the device detects address transitions on an address bus. The address transition detection circuit enables circuits for processing the new data for the new address transition. Thereafter, the device processes the new address. The address transition detection and power reduction circuit then disables the circuits for processing the address transition to reduce DC power consumption until the next address transition is detected.

Methods and apparatus for using address transition detection to reduce

A noise filter to eliminate short, multiple pulses output from an address transition detection ('ATD') circuit caused by address line noise occurring during a read operation of a nonvolatile semiconductor memory. The ATD circuit includes a pulse summation circuit. Each address line sends an input pulse to the pulse summation circuit when the address bit corresponding to the address line changes. The pulse summation circuit adds and extends the input pulses to form output pulses. Pulse extension is performed by a delay chain formed by NAND and NOR gates. Each output pulse begins after a first predetermined time from the leading edge of an input pulse. The delay chain is set on the leading edge of each input pulse. The trailing edge of each input pulse determines when the delay chain will begin to reset. The extended pulse ends after a delay caused by the delay chain unless a subsequent pulse leading edge occurs within a second predetermined time from each trailing edge. In this way, short, multiple input pulses are turned into one long continuous output pulse. This prevents the sending of short pulses into sensing circuits where they would cause the wrong data to be sensed and latched.

Address transition detection noise filter in pulse summation circuit for

A mechanism to change the functionality of a state machine used to control operation of an EPROM device. The mechanism is programmed to generate logic level signals which are input to combinatorial logic used to implement the state machine to cause the state machine to operate with a predetermined number of wait states (typically on, two or three wait states) depending on the programming applied to the mechanism. The mechanism utilizes EPROM cells which are covered by a shield so that once programmed, they cannot be erased. The programming is performed after the part has been manufactured, but before shipment to a customer who, upon receipt of the part programs the EPROM in the usual manner. The programmed EPROM can then be erased nd reprogrammed without affecting the programming defining the number of wait states generated during operation of the state machine.

Apparatus for selecting mumber of wait states in a burst EPROM

Circuitry which when combined with an EPROM in a single integrated circuit for connection to a microprocessor which provides suitable signals utilized by the additional circuitry to provude faster access to the code or data stored in the EPROM than can be accomplished without such additional circuitry by providing zero wait state burst performance. A state machine is utilized to manage the interface between the microprocessor and the burst EPROM.

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Rancho Cordova, CA, United States of America

David A Leak