International Business Machines Corporation

David A Kummer

Jesus A Saenz

Lewis C Eggebrecht

Mark Edward Dean

Stephen W Trynosky

James Arthur Brewer

Darwin P Rackley

Gary Edward Webb

Patricia P McHugh

In a bit mapped raster scan digital display system, a number of maps each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares all bits of the two bytes of data with the associated bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.

Raster scan digital display system with digital comparator means

Extended addressing apparatus and method for direct storage access

A microcomputer includes a main memory system which is accessed, substantially independantly, by the CPU and a subsystem, for example a video display subsystem. The memory system comprises a base memory and an optical add on expansion memory. When only the base memory is installed, consecutive locations have consecutively numbered addresses, and both the CPU and subsystem access individual locations. When both memories are installed, one has even numbered addresses and the other odd numbered addresses. With both memories installed, the CPU still accesses individual locations, but the subsystem addresses even addresses to obtain, for each access, data from the even address and the next higher odd address, thereby accessing a location in both memories. Thus the memory bandwidth for the subsystem is effectively doubled when the expansion memory is installed.

Memory access system for a computer system adapted to accept a memory

In a microcomputer system having a main memory accessed by both the CPU and the CRT controller, a page register system receives page bits defining both CPU and CRT pages from the CPU. The CPU page bits are combined with lower order address bits from the CPU for CPU access cycles, and the CRT page bits are combined with lower order address bits from CRT controller for CRT access cycles. Both the CPU and CRT controller can access any of the pages in the memory. For compatibility with higher level systems, the CPU may provide addresses in a range outside the range of addresses for the memory. When a decoder detects such addresses, it directs CPU address bits, corresponding in order to the CPU page bits, to address the memory instead of the CPU page bits.

Memory paging system in a microcomputer

A microcomputer system employs internal read-only memory devices and external read-only memory devices in pluggable cartridges. Each cartridge includes jumper links in leads from the external memories through the cartridge socket to a memory select unit and jumper links in leads leading from earth through the cartridge socket to enable inputs of the internal memories. By linking selected ones of the jumper links in the cartridge, the external memory can be used as an add-on memory or as a base memory replacing the internal memory.

Microcomputer system employing program cartridges

A raster scan display system includes a plurality of storage maps. These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide color signals from which color video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.

Raster scan display system

In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.

Raster scan digital display system

In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a 'D-type' latch (24) whose output, in turn, sets the highest priority DMA channel (0) request line (DREQ0), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACK0) indicating the cycle is completed.

Refresh circuit for dynamic memory of a data processor employing a

Two controller units controlling a single input/output device such as a cathode ray tube (CRT) are synchronized by a command signal. Upon appearance of the command signal, the slave controller unit, which may have been running unsynchronized with the master controller, is stopped at the time for vertical retrace and remains stopped until vertical retrace time for the master controller. At this point, the slave controller is restarted in synchronism with the master controller and remains synchronized so long as both master and slave receive the same clock and the same screen refresh parameters.

Synchronization of CRT controller chips

A 3.58 MHz subcarrier signal and a 14.318 MHz clock signal are applied to three flipflops (50, 52 and 54) in such a manner that there appears on the output terminals (Q and Q) of the latches individual phase-shifted subcarriers having relative phases of 0.degree., 180.degree., 90.degree., 270.degree., 135.degree. and 315.degree. , respectively, representing the colors yellow, blue, red, cyan, magenta and green, respectively. Computer-generated digital color signals (+BLUE, +GREEN, +RED) are applied to the switching inputs (A, B, C) of a multiplexer (56) in order selectively to switch to the output of the multiplexer individual ones of the phase-shifted subcarriers in accordance with the code represented by the digital color signals. The individual subcarriers are combined in a summing circuit (62, 64) with television synchronizing and blanking pulses to produce a composite video color signal which is directly compatible with a conventional composite monitor and, after R.F. modulation, with a conventional television receiver. Brighter versions of the colors are obtained by increasing the direct current level (+INTENSITY) at the summing circuit.

Composite video color signal generation from digital color signals

A central processing unit (10) loads a border register (36) with four color bits representing digital color signals to be used in determining the color of only the border area (40) surrounding the video area (42) of a cathode ray tube display screen (44). A BORDER CONTROL TIME signal is generated at the appropriate times in the horizontal and vertical scanning periods of the cathode ray tube to apply the digital color border signals (R, G, G, I) to a composite video signal generator (38) which generates the composite video signal for a TV set (14) or a TV monitor.

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Boca Raton, FL, United States of America

David A Kummer