International Business Machines Corporation

David A Kiesling

Edward B Eichelberger

Francis H Chan

Evan Ezra Davidson

William M Chu

William J Scarpero, Jr

Mark D Mayo

Arnold E Barish

John W Hartman

Charles W Cha

Walter A Svarczkopf

A low power push pull off chip driver for differential cascode current circuitry is described that includes the collectors of a differential pair directly coupled to bases of a push pull driver and level shifters coupled to the input of the differential pair to prevent saturation of the differential pair.

Low power push pull driver

A circuit for testing a differential current switching logic circuit of the type including: a bias potential, two resistors connected to the bias potential, and apparatus responsive to an input signal for sinking a first current through a selected one of the resistors so as to generate first and second differential output signals at the resistors. The circuit includes first, second, and third transistors, each having first and second terminals for conducting a current responsive to a signal applied to a control terminal. Apparatus are provided for supplying a current. The first transistor has its first terminal connected to the current supplying means, and its second terminal connected to a circuit node. The second transistor has its first terminal connected to the circuit node, its second terminal connected to the bias potential, and its control terminal connected to sense the potential at a selected one of the resistors. The third transistor has its first terminal connected to the circuit node, its second terminal connected to the selected resistor, and its control terminal connected to sense the potential at the other of the resistors. The circuit functions to sense the potential difference between the first and second differential output signals. When the potential difference is less than a predetermined level, a second current is sunk through the one resistor so as to lower the potential of the output signal associated with the one resistor relative to the potential of the output signal associated with the other resistor.

Method and apparatus for detecting faults in differential current

Disclosed is a test system having circuitry for reducing off-chip driver switching (delta I) noise. The test system employs a tester connected to and electrically testing an integrated circuit chip. The integrated circuit chip has a plurality of input terminals for receiving an electrical test pattern from the tester. The integrated circuit chip also includes a plurality of output driver circuits having outputs connected to the tester. The test system is characterized in that the integrated circuit chip includes a driver sequencing network under control of the tester for sequentially conditioning the off-chip driver circuits for possible switching.

Noise reduction during testing of integrated circuit chips

Integrated circuit logic chips often oscillate during testing because the large unbypassed inductance of the test fixture causes off-chip driver switching noise to be fed back to the logic chip power supply. Oscillation may be prevented by adding an inhibit receiver and an off-chip driver inhibit network to the logic chip. The off-chip driver inhibit network provides a fan out path from the inhibit receiver to each off-chip driver. In response to an inhibit signal applied to the inhibit receiver, the inhibit network forces each of the off-chip drivers to the same logical state, the logic state being the natural logic state assumed by the off-chip drivers upon initial application of power to the chip. The driver inhibit receiver and inhibit network are employed to prevent oscillation at chip power-on, during driver and receiver parametric testing and during input test pattern tests.

Oscillation prevention during testing of integrated circuit logic chips

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Pleasant Valley, NY, United States of America

David A Kiesling