Micron Technology Incorporated

Lodestar Licensing Group LLC

David A Kewley

Adam L Olson

Raju Ahmed

Radhakrishna Kotti

William R Brown

Xiaosong Zhang

Michael D Hyatt

Vishal Sipani

Dave Pratt

Trupti D Gawai

Jason Reece

Kyle Armstrong

Michael Dean Van Patten

David S Pratt

Rohit Kothari

Jason C McFarland

Dale Collins

Stephen W Russell

Ming-Chuan Yang

Brian J Cleereman

Tim H Bossart

Nikolay A Mirin

Anthony C Krauth

Rex Stone

Biow Hiem Ong

Brian R Watson

Jenna L Russon

Ahmed M Elsied

Chelsea M Jordan

Tien Minh Quan Tran

Yongjun Jeff Hu

Anton J deVillers

Matthew J King

Scott L Light

Robert J Hanson

Daniel Billingsley

Suresh Ramarajan

Jianming Zhou

Merri Lyn Carlson

Gurpreet S Lugani

Prasanna Srinivasan

Frank Speetjens

Keen Wah Chow

Neal L Davis

Yung-Ta Sung

Michael J Irwin

Kok Siak Tang

Chao Zhu

Md Zakir Ullah

Hui Chin Chong

Md Zahid Hossain

Mohammad Moydul Islam

Zhigang Yang

Yuan He

Lifang Xu

Justin B Dorhout

Chandra S Tiwari

Yi Hu

Matthew Park

Tom Jibu John

Kevin Lee Baker

Shruthi Kumara Vadivel

Matthew Holland

Michael E Koltonski

Joel D Peterson

Michael J Gossman

Bo Zhao

Martin Jared Barclay

Hong Chen

Aaron M Lowe

Deep Panjwani

Kah Sing Chooi

Zhen Feng Yow

Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

Assemblies having conductive interconnects which are laterally and vertically offset relative to one another

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure. A distance between the first pillar structures and the slot structures is substantially equal to a distance between the second pillar structures and the slot structures.

Microelectronic devices including slot structures, and related electronic systems and methods of forming the microelectronic devices

A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

Microelectronic devices including stadium structures

Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

Methods for forming conductive vias, and associated devices and systems

Integrated circuitry comprises a horizontally-elongated insulative wall directly above a conductive node. The wall comprises insulative material. A conductive via extends through the wall to the conductive node. A conductive line is directly above the wall and directly above the conductive via. The conductive via directly electrically couples together the conductive line with the conductive node. Insulator material is longitudinally-along laterally-opposing sides of the wall. An interface of the insulative material of the wall and the insulator material are on each of the laterally-opposing sides of the wall. Other embodiments, including method, are disclosed.

Integrated circuitry, array of cross-point memory cells, method used in forming integrated circuitry

Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.

Methods of forming a staircase structure

Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

Microelectronic devices with tiered decks of aligned pillars exhibiting bending and related methods

Assemblies having conductive interconnects which are laterally and vertically offset relative to one another and methods of forming assemblies having conductive interconnects which are laterally and vertically offset relative to one another

An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

Apparatus and memory device including conductive lines and contacts, and methods of forming an apparatus including conductive lines and contacts

Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

Conductive interconnects and methods of forming conductive interconnects

Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, 'pillar density' being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

Microelectronic devices with tiered decks of differing pillar density and related methods and systems

Growing community of inventors

Boise, ID, United States of America

David A Kewley