Hewlett-packard Development Company, L.p.

David A J Webb, Jr

Richard Eugene Kessler

Steve Lang

Samuel Hammond Duncan

Aaron T Spink

David W Hartwell

Shubhendu Sekhar Mukherjee

A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks. The I/O bridge ASIC includes a DMA device that supports both in-order and out-of-order DMA read and write streams of data blocks. An in-order stream of reads of data blocks performed by the DMA device always results in the DMA device receiving coherent data blocks that do not have to be written back to the memory module.

Scalable efficient I/O port protocol

A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster. All processors within the cluster invalidate a local copy of the shared data if it exists and once the master processor receives acknowledgements from all processors in the cluster, the master processor sends an invalidate acknowledgment message to the processor that originally requested the exclusive rights to the shared data. The cache coherency is scalable and may be implemented using the hybrid point-to-point/broadcast scheme or a conventional point-to-point only directory-based invalidate scheme.

Broadcast invalidate scheme

A system and method is disclosed for reducing network message passing latency in a distributed multiprocessing computer system that contains a plurality of microprocessors in a computer network, each microprocessor including router logic to route message packets prioritized in importance by the type of message packet, age of the message packet, and the source of the message packet. The microprocessors each include a plurality of network input ports connected to corresponding local arbiters in the router. The local arbiters are each able to select a message packet from the message packets waiting at the associated network input port. Microprocessor input ports and microprocessor output ports in the microprocessor allow the exchange of message packets between hardware functional units in the microprocessor and between the microprocessors. The microprocessor input ports are similarly each coupled to corresponding local arbiters in the router. Each of the local arbiters is able to select a message packet among the message packets waiting at the microprocessor input port. Global arbiters in the router connected to the network output ports and microprocessor output ports select a message packet from message packets nominated by the local arbiters of the network input ports and microprocessor input ports. The local arbiters connected to each network input port or microprocessor input port will request service from a output port global arbiter for a message packet based on the message packet type if the message packet is ready to be dispatched.

Growing community of inventors

Groton, MA, United States of America

David A J Webb, Jr