Intel Corporation

David A Helder

Kalyan Muthukumar

The present invention provides a mechanism that facilitates speculative execution of instructions within software-pipelined loops. In accordance with one embodiment of the invention, a software-pipelined loop is initialized with a speculative instruction deactivated. At least one initiation interval of the software-pipelined loop is executed, and the speculative instruction is activated. Subsequent initiation intervals of the software-pipelined loop are then executed.

Mechanism to avoid explicit prologs in software pipelined do-while loops

The present invention provides a mechanism for implementing compare speculation in software pipelined loops. A data dependency graph (DDG) is generated for a loop that includes a control compare instruction, a compare instruction and a non-speculative instruction that depends directly or indirectly on the compare instruction. A loop-carried edge between the control compare instruction and the compare instruction is replaced by a loop-carried edge between the control compare instruction and the non-speculative instruction. If the compare instruction is speculated when the loop is modulo-scheduled, any load instruction that depends on the compare is converted to a speculative load, and a loop-carried edge is added between the control compare and a check instruction associated with the speculative load. A loop-independent edge is also added between the check instruction and the non-speculative instruction if the non-speculative instruction also depends on the load.

Growing community of inventors

Holland, MI, United States of America

David A Helder