Apple Inc.

Other

David A Hartley

Arthur L Spence

Paolo Sacchetto

Peter F Holland

Brijesh Tripathi

Inder M Sodhi

Joseph T DiBene, Ii

Chengrui Le

Jason N Gomez

Kevin W Sliech

Axel B Schumacher

In an embodiment, an electronic device includes an electronic display. The electronic display provides a programmable latency period in response to receiving a first image frame corresponding to first image frame data. The electronic display also displays the first image frame after the programmable latency period and during display of the first image frame, receives a second image frame corresponding to second image frame data. The electronic display also repeats display of the first image frame in response to receiving the second image frame.

Preemptive refresh for reduced display judder

In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.

Power management architecture

Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.

Variable frame refresh rate

A saddle rack has a plurality of flat planar pieces which are stackable one on the other for storage. The pieces can temporarily be connected together into a self supporting saddle rack. Included among the pieces are first and second vertical end elements, a lower horizontal cross member and a plurality of upper horizontal cross members. The lower horizontal cross member has ends with each of the ends temporarily connectable to one of the end elements. Each of the upper horizontal have ends with each of the ends temporarily connectable to the top of one of the end elements.

Collapsible stackable saddle rack

Growing community of inventors

Santa Cruz, CA, United States of America

David A Hartley